公开(公告)号：US09187312B2

公开(公告)日：2015-11-17

申请号：US14202756

申请日：2014-03-10

申请人： Raytheon Company

发明人： Roland Gooch ,  Buu Diep ,  Thomas Allan Kocian ,  Stephen H. Black ,  Adam M. Kennedy

IPC分类号： H01L21/30 ,  B81B7/00 ,  B81C1/00 ,  H01L23/053 ,  H01L23/00

CPC分类号： B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

公开(公告)号：US20150279755A1

公开(公告)日：2015-10-01

申请号：US14736042

申请日：2015-06-10

申请人： RAYTHEON COMPANY

发明人： Roland W. Gooch ,  Buu Q. Diep ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas A. Kocian

IPC分类号： H01L23/10 ,  H01L23/26 ,  H01L21/52

CPC分类号： H01L23/10 ,  B81B7/0038 ,  B81B2201/0207 ,  B81C1/00269 ,  B81C2203/035 ,  H01L21/52 ,  H01L21/76841 ,  H01L23/26 ,  H01L23/49866 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

公开(公告)号：US20150271403A1

公开(公告)日：2015-09-24

申请号：US13768505

申请日：2013-02-15

申请人： RAYTHEON COMPANY

发明人： Stephen H. Black ,  Paolo Masini

IPC分类号： H04N5/232 ,  G01J1/02 ,  H04N5/33 ,  G01P15/00

CPC分类号： H04N5/23241 ,  G01J1/0228 ,  G01J2001/0257 ,  G01P15/00 ,  G01P15/0891 ,  H04N5/33

摘要： According to one aspect, embodiments herein provide a sensing device comprising an accelerometer configured to monitor acceleration of the sensing device and provide acceleration information including a value of the acceleration of the sensing device, and an Integrated Circuit (IC) coupled to the accelerometer, the IC configured to receive the acceleration information from the accelerometer and render the sensing device permanently inoperable in response to the value of the acceleration of the sensing device exceeding a threshold indicative of a military application of the sensing device.

摘要翻译： 根据一个方面，本文的实施例提供一种感测装置，其包括加速度计，该加速度计被配置为监测感测装置的加速度并提供包括感测装置的加速度值的加速度信息，以及耦合到加速度计的集成电路（IC） IC被配置为从加速度计接收加速度信息并且使得感测装置响应于感测装置的加速度的值超过表示感测装置的军事应用的阈值而永久地不可操作。

公开(公告)号：US09093444B2

公开(公告)日：2015-07-28

申请号：US13939400

申请日：2013-07-11

申请人： Raytheon Company

发明人： Roland W. Gooch ,  Buu Q. Diep ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas Allan Kocian

IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L23/02 ,  H01L23/06 ,  H01L23/498 ,  H01L21/768 ,  B81B7/00 ,  B81C1/00 ,  H01L23/26 ,  H01L27/146

CPC分类号： H01L23/10 ,  B81B7/0038 ,  B81B2201/0207 ,  B81C1/00269 ,  B81C2203/035 ,  H01L21/52 ,  H01L21/76841 ,  H01L23/26 ,  H01L23/49866 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

摘要翻译： 电子装置及其制造方法。 一种或多种方法可以包括提供具有空腔和围绕空腔的表面的盖晶片和具有检测器装置和参考装置的装置晶片。 在某些实例中，可以将钛材料的阻焊层沉积到盖晶片的表面上。 可以进一步激活钛材料的阻焊层作为吸气剂。 在各种示例中，盖晶片和器件晶片可以使用焊料接合在一起，并且钛材料的阻焊层可以防止焊料接触盖晶片的表面。

公开(公告)号：US08736045B1

公开(公告)日：2014-05-27

申请号：US13667458

申请日：2012-11-02

申请人： Raytheon Company

发明人： Roland Gooch ,  Buu Diep ,  Thomas Allan Kocian ,  Stephen H. Black ,  Allan M. Kennedy

IPC分类号： H01L23/12

CPC分类号： B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

摘要翻译： 一种形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括残留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的所述第一和第二组的组合厚度在所述器件晶片和所述盖晶片接合时限定了整合的接合间隙控制结构。

公开(公告)号：US20140124899A1

公开(公告)日：2014-05-08

申请号：US13667458

申请日：2012-11-02

申请人： RAYTHEON COMPANY

发明人： Roland Gooch ,  Buu Diep ,  Thomas Allan Kocian ,  Stephen H. Black ,  Adam M. Kennedy

IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L21/56

CPC分类号： B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.