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31.发明授权Memory management unit for developing multiple physical addresses in parallel for use in a cache memory 失效用于并行开发多个物理地址以用于高速缓冲存储器的存储器管理单元
公开(公告)号：US4378591A
公开(公告)日：1983-03-29
申请号：US221852
申请日：1980-12-31
申请人： Richard A. Lemay
发明人： Richard A. Lemay
CPC分类号： G06F12/0802
摘要： A cache memory for use in a data processing system wherein data words are identified by either an odd or an even address number and wherein system elements request the transfer of data words with the cache memory by supplying either an odd or an even memory request address number with a memory request, the cache memory including a first pllurality of addressable memory locations for storing data words associated with odd address numbers and a second plurality of memory locations for storing data words associated with even address numbers, and an adder for incrementing a memory request address number by one to generate the address number of the next successively stored data word to permit a set of memory address drivers to control the addressing and transferring of a data word stored in the first memory module and associated with an odd address number simultaneously with the addressing and transferring of a data word stored in the second memory module and addressed by an even address number.
摘要翻译： 一种用于数据处理系统的高速缓冲存储器，其中数据字由奇数或偶数地址号码标识，并且其中系统元件通过提供奇数或偶数存储器请求地址号码请求与高速缓存存储器的数据字的传送 在存储器请求中，高速缓冲存储器包括用于存储与奇数地址号码相关联的数据字的第一多种可寻址存储器位置和用于存储与偶数地址号码相关联的数据字的第二多个存储单元，以及用于递增存储器请求的加法器 地址编号1以产生下一个连续存储的数据字的地址号，以允许一组存储器地址驱动器控制存储在第一存储器模块中并与奇数地址号码相关联的数据字的寻址和传送，同时与 寻址和传送存储在第二存储器模块中并由偶数地址nu寻址的数据字 mber
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32.发明授权Communications processor employing line-dedicated memory tables for supervising data transfers 失效通信处理器采用行专用存储表来监控数据传输
公开(公告)号：US4261033A
公开(公告)日：1981-04-07
申请号：US760782
申请日：1977-01-19
CPC分类号： G06F13/34 , G06F13/385
摘要： A communications processor is coupled between a main memory and a plurality of communications channels and with a central processing unit and includes control mechanisms for processing the transfer of information between the processor and the main memory with minimum interruption of the central processing unit. The processor further includes control tables and a plurality of control routines enabling the processing of the transfer of the information between the processor and the channels. The routines are unique to the communications channel characteristics of the device coupled with the channel being serviced and is configurable to reflect any changes made in such characteristics.
摘要翻译： 通信处理器耦合在主存储器和多个通信信道之间并且与中央处理单元相连，并且包括用于在中央处理单元的中断最小的情况下处理处理器和主存储器之间的信息传送的控制机制。 处理器还包括控制表和多个控制例程，使得能够处理处理器和通道之间的信息传送。 这些例程对于与被维护的信道耦合的设备的通信信道特性是唯一的，并且可配置为反映在这些特性中所做的任何改变。
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公开(公告)号：US4236203A
公开(公告)日：1980-11-25
申请号：US867270
申请日：1978-01-05
CPC分类号： G06F13/368 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.
摘要翻译： 在包括公共总线的系统中，诸如数据处理系统的用于传送信息的多个单元连接到该公共总线，在异步生成的总线传送周期期间，信息可以由最高优先级请求单元传送。 逻辑被提供用于实现多次提取操作，其中主单元在第一总线传送周期期间从从单元请求多个信息字可以在一系列随后从站产生的总线周期期间从从单元接收这些信息。 逻辑被提供用于使得任何其他单元能够在第一周期与从单元响应的最后周期之间的时间内通过公共总线进行通信，从而使得至少两对单元能够分别在交织的 方式。
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34.发明授权Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus 失效通过异步公共总线网络耦合数据处理设备进行数据传输的同步技术
公开(公告)号：US4050097A
公开(公告)日：1977-09-20
申请号：US727194
申请日：1976-09-27
申请人： Ming T. Miu , Virendra S. Negi , Richard A. Lemay
发明人： Ming T. Miu , Virendra S. Negi , Richard A. Lemay
CPC分类号： G06F1/08 , G06F13/4213
摘要： Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.
摘要翻译： 数据传输同步在数据处理系统中通过传送单元实现，每当传输尝试时，能够进行时钟周期失速机制，在接收到来自接收单元的预定响应时禁用这种机制，实际产生时钟周期失速的机制如果 这种预定响应被延迟超过时钟周期的持续时间。 此外，在预期接收到信息之前，在接收单元中启用这种停止机制，并且如果这样的响应如此延迟，则实际上产生时钟周期停滞。
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35.发明授权Power-on sequencing apparatus for initializing and testing a system processing unit 失效用于初始化和测试系统处理单元的上电排序装置
公开(公告)号：US5491790A
公开(公告)日：1996-02-13
申请号：US231856
申请日：1994-04-22
IPC分类号： G06F1/00 , G06F9/06 , G06F9/445 , G06F11/22 , G06F11/267
CPC分类号： G06F11/2236 , G06F11/22 , G06F9/4403
摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.
摘要翻译： 除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。 处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。 在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。
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公开(公告)号：US5341501A
公开(公告)日：1994-08-23
申请号：US771582
申请日：1991-10-04
IPC分类号： G06F13/368 , G06F9/46
CPC分类号： G06F13/368
摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.
摘要翻译： 高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。 电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。 所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟 当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。
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公开(公告)号：US5293384A
公开(公告)日：1994-03-08
申请号：US771581
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay
发明人： James W. Keeley , Richard A. Lemay
CPC分类号： G06F13/4217
摘要： A high performance microprocessor has associated therewith, protocol monitoring apparatus for monitoring all of the commands issued by the microprocessor and detecting when the protocol was not completed properly or completed within certain preestablished periods of time. When the monitor/timing circuits detect a protocol error, the monitoring apparatus operates to generate an output control signal which unwedges the microprocessor enabling it to continue further processing. Additionally, the monitoring apparatus includes a register for storing the address and command that the microprocessor was executing at the time of the protocol error. The same register is also used to capture address and command information for any other type of error.
摘要翻译： 高性能微处理器与其相关联，用于监视由微处理器发出的所有命令的协议监视装置，以及检测协议何时未正确完成或在某些预先建立的时间段内完成。 当监视器/定时电路检测到协议错误时，监视装置操作以产生输出控制信号，该输出控制信号使微处理器能够继续进行进一步的处理。 此外，监视装置包括用于存储微处理器在协议错误时执行的地址和命令的寄存器。 相同的寄存器也用于捕获任何其他类型错误的地址和命令信息。
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公开(公告)号：US4254462A
公开(公告)日：1981-03-03
申请号：US911635
申请日：1978-06-01
CPC分类号： G06F13/385
摘要： A hardware/firmware control system is disclosed for accommodating the concurrent bi-directional transfer of information between a communications channel such as a telephone line and a communications processor in a data processing system.
摘要翻译： 公开了一种硬件/固件控制系统，用于在诸如电话线的通信信道和数据处理系统中的通信处理器之间容纳信息的同时双向传送。
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公开(公告)号：US4181974A
公开(公告)日：1980-01-01
申请号：US867266
申请日：1978-01-05
申请人： Richard A. Lemay , John L. Curley
发明人： Richard A. Lemay , John L. Curley
CPC分类号： G06F13/368 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred during asynchronously generated information transfer cycles. Logic is provided for enabling a first unit to transfer first information to a second unit during a first request transfer cycle requesting that the second unit transfer second information to the first unit during a later first response transfer cycle. Logic is also provided to enable the first unit to transfer third information to a third unit during a second request transfer cycle requesting that the third unit transfer fourth information to the first unit during a later second response transfer cycle. Logic is provided that enable the first unit to transfer the third information before receiving the second information and logic is further provided that enables the first unit to receive the second information before or after receiving the fourth information. Logic is provided for enabling any other unit to communicate over the common bus during the time between the first request transfer cycle and the latest transfer cycle associated with the transfer of the second and fourth information.
摘要翻译： 在包括公共总线的系统中，诸如数据处理系统之类的多个单元被连接用于信息传送的公共总线，可以在异步生成的信息传送周期期间传送信息。 逻辑被提供用于使得第一单元能够在第一请求传送周期期间将第一信息传送到第二单元，请求第二单元在稍后的第一响应传送周期期间将第二信息传送到第一单元。 还提供逻辑以使得第一单元能够在第二请求传送周期期间将第三信息传送到第三单元，请求第三单元在稍后的第二响应传送周期期间将第四信息传送到第一单元。 提供逻辑，使得第一单元能够在接收第二信息之前传送第三信息，并且进一步提供使第一单元能够在接收第四信息之前或之后接收第二信息的逻辑。 逻辑被提供用于使得任何其他单元能够在第一请求传送周期与与第二和第四信息的传送相关联的最新传送周期之间的时间内通过公共总线进行通信。
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40.发明授权
公开(公告)号：US4133030A
公开(公告)日：1979-01-02
申请号：US760773
申请日：1977-01-19
申请人： Robert E. Huettner , John P. Grandmaison , John H. Vernon , Richard A. Lemay , Edward Beauchemin
发明人： Robert E. Huettner , John P. Grandmaison , John H. Vernon , Richard A. Lemay , Edward Beauchemin
CPC分类号： G06F13/385 , G06F13/122
摘要： Data is transferred between a main memory in a data processing system and communication channels under the control of communications control blocks provided in an auxiliary memory, each of which control blocks includes a starting address, range and status information so as to enable the transfer of data to data blocks included in the main memory as indicated by the starting address in the control blocks. A predetermined number of control blocks is allocated in the auxiliary memory for each communications channel and the transfer of all such data is performed utilizing as many of the predetermined number of control blocks as required for the channel until the transfer is complete as indicated by the last such control block utilized in the transfer. Control blocks are loaded in the auxiliary memory under control of the central processor of the system and are periodically accessed by the processor to determine the status of data transfer operations. Circuits are provided for preventing the loading in the auxiliary memory of more than the predetermined number of control blocks for a channel and for preventing the execution of a status inquiry for a channel when no control blocks for that channel are in the active state.
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