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    Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus
    1.
    发明授权
    Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus 失效
    通过异步公共总线网络耦合数据处理设备进行数据传输的同步技术

    公开(公告)号：US4050097A

    公开(公告)日：1977-09-20

    申请号：US727194

    申请日：1976-09-27

    申请人： Ming T. Miu ,  Virendra S. Negi ,  Richard A. Lemay

    发明人： Ming T. Miu ,  Virendra S. Negi ,  Richard A. Lemay

    IPC分类号： G06F1/08 ,  G06F13/42 ,  G06F1/04

    CPC分类号： G06F1/08 ,  G06F13/4213

    摘要： Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.

    摘要翻译： 数据传输同步在数据处理系统中通过传送单元实现，每当传输尝试时，能够进行时钟周期失速机制，在接收到来自接收单元的预定响应时禁用这种机制，实际产生时钟周期失速的机制如果 这种预定响应被延迟超过时钟周期的持续时间。 此外，在预期接收到信息之前，在接收单元中启用这种停止机制，并且如果这样的响应如此延迟，则实际上产生时钟周期停滞。

    Executing programs of a first system on a second system
    2.
    发明授权
    Executing programs of a first system on a second system 失效
    在第二个系统上执行第一个系统的程序

    公开(公告)号：US5983012A

    公开(公告)日：1999-11-09

    申请号：US128456

    申请日：1993-09-28

    申请人： Richard S. Bianchi ,  Dennis R. Flynn ,  Marcia T. Fogelgren ,  Richard A. Lemay ,  Mary E. Tovell ,  William E. Woods

    发明人： Richard S. Bianchi ,  Dennis R. Flynn ,  Marcia T. Fogelgren ,  Richard A. Lemay ,  Mary E. Tovell ,  William E. Woods

    IPC分类号： G06F1/00 ,  G06F9/455 ,  G06F9/46 ,  G06F13/10 ,  G06F21/00

    CPC分类号： G06F21/31 ,  G06F13/10 ,  G06F13/105 ,  G06F21/6281 ,  G06F9/45537 ,  G06F2221/2105

    摘要： An emulator executes on a second data processing system as a second system user level process including a first system user level program, a first system executive program, and first system user and executive tasks. An emulator level is interposed between the second system user level process and a kernel level and contains pseudo device drivers. Each pseudo device driver corresponds to a first system input/output device. The kernel level includes kernel processes, each kernel process corresponding to a pseudo device driver. The second system hardware platform includes a plurality of second system input/output devices, wherein each second system input output device corresponds to a kernel process. Each combination of a pseudo device driver, a corresponding kernel process and a corresponding second system input/output device executes in a second system process and emulates the operations of a corresponding first system input/output task and the corresponding first system input/output device. The pseudo device drivers are constructed of a plurality of pseudo device queues, a return queue and a queue manager.

    摘要翻译： 模拟器在第二数据处理系统上执行，作为包括第一系统用户级程序，第一系统执行程序以及第一系统用户和执行任务的第二系统用户级进程。 在第二系统用户级别进程和内核级别之间插入一个仿真器级别，并包含伪设备驱动程序。 每个伪设备驱动程序对应于第一系统输入/输出设备。 内核级别包括内核进程，每个内核进程对应一个伪设备驱动程序。 第二系统硬件平台包括多个第二系统输入/输出设备，其中每个第二系统输入输出设备对应于内核进程。 伪设备驱动器，相应的内核进程和对应的第二系统输入/输出设备的每个组合在第二系统进程中执行并且模拟对应的第一系统输入/输出任务和对应的第一系统输入/输出设备的操作。 伪设备驱动程序由多个伪设备队列，返回队列和队列管理器构成。

    Programmable system bus priority network
    3.
    发明授权
    Programmable system bus priority network 失效
    可编程系统总线优先网络

    公开(公告)号：US5446847A

    公开(公告)日：1995-08-29

    申请号：US531

    申请日：1993-01-04

    申请人： James W. Keeley ,  George J. Barlow ,  Richard A. Lemay

    发明人： James W. Keeley ,  George J. Barlow ,  Richard A. Lemay

    IPC分类号： G06F13/372 ,  G06F13/18

    CPC分类号： G06F13/372

    摘要： A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.

    摘要翻译： 总线接口优先级网络通过多个不同类型的请求者提供对系统总线的访问，作为它们需要处理的事务的类型的函数。 该网络包括用于识别请求者的类型的可编程电路，并且基于请求者类型选择访问系统总线的延迟，从而消除了对最慢请求者调整定时的需要。

    Data selection matrix
    6.
    发明授权
    Data selection matrix 失效
    数据选择矩阵

    公开(公告)号：US4935737A

    公开(公告)日：1990-06-19

    申请号：US927632

    申请日：1986-11-05

    申请人： Kenneth J. Izbicki ,  William E. Woods ,  Richard A. Lemay

    发明人： Kenneth J. Izbicki ,  William E. Woods ,  Richard A. Lemay

    IPC分类号： G06F7/76

    CPC分类号： G06F7/76

    摘要： A data selection matrix is disclosed which uses a plurality of programmed array logic (PAL) units having input thereto portions of binary words from a plurality of sources, the PALs being responsive to control words also input thereto to jointly select one of said sources of binary words and to select the arrangement of the portions of the binary words being input thereto from the selected source of binary words.

    摘要翻译： 公开了一种数据选择矩阵，其使用多个编程的阵列逻辑（PAL）单元，其具有从多个源输入二进制字的部分，PAL响应于也输入到其的控制字来共同选择所述二进制源之一 并且从所选择的二进制字源中选择从其输入的二进制字的部分的排列。

    Time partitioned bus arrangement
    7.
    发明授权
    Time partitioned bus arrangement 失效
    时间分配总线安排

    公开(公告)号：US4775929A

    公开(公告)日：1988-10-04

    申请号：US917940

    申请日：1986-10-14

    申请人： Kenneth J. Izbicki ,  William E. Woods ,  Richard A. Lemay ,  Steven A. Taque

    发明人： Kenneth J. Izbicki ,  William E. Woods ,  Richard A. Lemay ,  Steven A. Taque

    IPC分类号： G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/4217

    摘要： What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement. Some of the processor circuits have a control lead input that is energized by the clock signal output from the system clock so that they accept information from one bus to which their input is connected during a first polarity portion of a clock cycle and return either unprocessed or processed information to another bus during a second polarity portion of a clock cycle.

    摘要翻译： 所公开的是用于计算机系统中的时间分配总线布置，其中其中不同的电路通过多个总线互连，并且操作使得可以从一个电路中读出要处理的信息，以某种方式在另一个电路中进行处理 并且处理的信息在计算机系统中的系统时钟的一个周期内被存储在相同或另一个电路中，并且不需要连接到总线的电路中的总线控制电路和总线接口。 一些电路的输入/输出仅连接到总线中的单个总线，而其他电路的输入连接到一个总线，其输出连接到不同的总线，而其他电路的输入或输出连接到 总线中的一个和其他输入/输出连接到总线布置外部的电路。 一些处理器电路具有由从系统时钟输出的时钟信号激励的控制引线输入，使得它们在时钟周期的第一极性部分期间接收来自其输入连接到的一个总线的信息，并返回未处理的或 在时钟周期的第二极性部分处理信息到另一个总线。

    Logic control system including cache memory for CPU-memory transfers
    8.
    发明授权
    Logic control system including cache memory for CPU-memory transfers 失效
    逻辑控制系统包括用于CPU存储器传输的缓存

    公开(公告)号：US4460959A

    公开(公告)日：1984-07-17

    申请号：US302904

    申请日：1981-09-16

    申请人： Richard A. Lemay ,  Philip E. Stanley ,  William E. Woods ,  David E. Cushing

    发明人： Richard A. Lemay ,  Philip E. Stanley ,  William E. Woods ,  David E. Cushing

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0859

    摘要： A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

    摘要翻译： 公开了一种由高速缓冲存储器系统和传送控制逻辑单元组成的逻辑控制系统，用于将来自中央存储器系统的程序信息和CPU（中央处理单元）指令的流程从公共通信总线上的CPU接收到CPU。 CPU和传输控制逻辑单元通过具有公共通信总线的高速缓冲存储器系统进行通信。 响应于对中央存储器系统的CPU请求，传输控制逻辑单元从高速缓冲存储器系统请求程序信息和指令，并以这样的方式呈现给CPU，以避免由信息传输延迟引起的CPU活动中断 。

    Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories
    9.
    发明授权
    Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories 失效
    通过选择性地将状态信号分组为输入并将待执行的命令分类为性能敏感和非敏感类别来组织状态机的方法

    公开(公告)号：US5375248A

    公开(公告)日：1994-12-20

    申请号：US99117

    申请日：1993-07-29

    申请人： Richard A. Lemay ,  Steven A. Tague ,  William E. Woods

    发明人： Richard A. Lemay ,  Steven A. Tague ,  William E. Woods

    IPC分类号： G06F9/26 ,  G06F9/28 ,  G06F13/00

    CPC分类号： G06F9/28 ,  G06F9/261

    摘要： A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.

    摘要翻译： 虚拟存储器单元（VMU）包括用于响应于从另一单元接收的命令来控制其操作的状态机。 状态机包括多个可编程阵列逻辑（PAL）装置，其被连接以从该装置的不同部分收集状态。 PAL设备的输出共同连接，并将第一地址输入提供给可寻址状态存储器。 状态存储器包括多个位置，每个位置存储限定不同机器状态的二进制代码。 根据状态信号和当前状态访问状态存储器位置，并依次使用生成用于执行接收到的命令的必需子命令。 状态机使得可以在接收到的命令的整体系统性能方面对其复杂性和紧迫性进行分类。