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    CA resistance variability prediction methodology
    31.
    发明授权
    CA resistance variability prediction methodology 有权
    CA抗性变异性预测方法

    公开(公告)号：US07831941B2

    公开(公告)日：2010-11-09

    申请号：US11968458

    申请日：2008-01-02

    申请人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    发明人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.

    摘要翻译： 一种用于获得电子电路中CA电阻改进预测的方法，特别是改进的CA电阻模型，适用于捕获大于预期的“超出规范”状态。 在一个实施例中，实现了一种新颖的分层方案，其编码为电路设计者提供了相当好的设计选项，用于处理大的CA变异性，如通过设计手册所看到的。 开发用于建模CA可变电阻现象影响的工具为开发人员提供了一种电阻模型，如常规已知的，使用新的CA模型Basis进行修改，包括新颖的CA内在电阻模型，以及新颖的CA布局分层模型。

    System for search and analysis of systematic defects in integrated circuits
    36.
    发明授权
    System for search and analysis of systematic defects in integrated circuits 有权
    集成电路系统缺陷的搜索和分析系统

    公开(公告)号：US07415695B2

    公开(公告)日：2008-08-19

    申请号：US11748575

    申请日：2007-05-15

    申请人： Bette L. Bergman Reuter ,  David L. DeMaris ,  Mark A. Lavin ,  William C. Leipold ,  Daniel N. Maynard ,  Maharaj Mukherjee

    发明人： Bette L. Bergman Reuter ,  David L. DeMaris ,  Mark A. Lavin ,  William C. Leipold ,  Daniel N. Maynard ,  Maharaj Mukherjee

    IPC分类号： G06F17/50

    CPC分类号： G06T7/001 ,  G06T2207/30148

    摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

    摘要翻译： 公开了一种定位集成电路系统缺陷的方法。 本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。 当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。 本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。 然后，本发明聚集特征向量以产生特征向量的索引。 在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。 该合并过程可以包括旋转和镜像缺陷区域中的形状。 本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。 然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。 然后，可以分析缺陷向量和特征向量之间的相似性和差异。

    PSEUDO-STRING BASED PATTERN RECOGNITION IN L3GO DESIGNS
    37.
    发明申请
    PSEUDO-STRING BASED PATTERN RECOGNITION IN L3GO DESIGNS 有权
    基于PSEUDO-STRING的图案识别在L3GO设计中

    公开(公告)号：US20080165192A1

    公开(公告)日：2008-07-10

    申请号：US11621383

    申请日：2007-01-09

    申请人： Ulrich A. Finkler ,  Mark A. Lavin ,  Robert T. Sayah

    发明人： Ulrich A. Finkler ,  Mark A. Lavin ,  Robert T. Sayah

    IPC分类号： G06T11/00

    CPC分类号： G06F17/5068 ,  G06F17/504 ,  G06F2217/12 ,  Y02P90/265

    摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a serialization system for converting an input region of glyph design data into a pseudo-string; and a pattern searching system that identifies matching patterns in the glyph design data by analyzing pseudo-strings generated by the serialization system. Pattern searching may include, e.g., predefined pattern searching and redundant pattern searching.

    摘要翻译： 一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。 提供一种系统，其包括用于将字形设计数据的输入区域转换为伪字符串的序列化系统; 以及通过分析由串行化系统生成的伪串来识别字形设计数据中的匹配模式的模式搜索系统。 模式搜索可以包括例如预定义模式搜索和冗余模式搜索。

    Lithographic process window optimization under complex constraints on edge placement
    39.
    发明授权
    Lithographic process window optimization under complex constraints on edge placement 有权
    边缘放置复杂约束下的平版印刷工艺窗口优化

    公开(公告)号：US07269817B2

    公开(公告)日：2007-09-11

    申请号：US10776901

    申请日：2004-02-10

    申请人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Daniel L. Ostapko ,  Alan E. Rosenbluth ,  Nakgeuon Seong

    发明人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Daniel L. Ostapko ,  Alan E. Rosenbluth ,  Nakgeuon Seong

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules. Pursuant to the method and system, lithographic capability and process windows are maximized to satisfy local circuit requirements and in order to achieve a maximally efficient layout. In this connection, there is employed a method utilizing a generalized lithographic process window as a measure when layout optimization is extended to a degree beyond that achieved by the simple fixed design rules which are applied to the design rules obtained is the advantage that a lithographic process window is determined purely through the calculation of image intensities and slopes, and as a result, the method can be quite rapid in application because it is possible to take advantage of known methods for rapid calculation of image intensity, and because there is obviated the need for geometrical shape processing during optimization.

    摘要翻译： 一种用于相对于光刻工艺窗口的布局优化的方法和系统，其有助于光刻约束被非局部化，以便赋予给定电路打印超过可以​​用常规简化设计规则达到的过程窗口的处理窗口的能力。 根据方法和系统，光刻能力和工艺窗口最大化，以满足局部电路要求，并实现最大限度的高效布局。 在这方面，采用一种利用广义平版印刷工艺窗口作为测量的方法，当布局优化扩展到超过通过简单的固定设计规则实现的程度时，应用于所获得的设计规则是光刻工艺的优点 通过计算图像强度和斜率来确定窗口，结果，该方法在应用中可以相当快速，因为可以利用已知的方法来快速计算图像强度，并且因为不需要 用于优化期间的几何形状处理。

    Method for performing monte-carlo simulations to predict overlay failures in integrated circuit designs
    40.
    发明授权
    Method for performing monte-carlo simulations to predict overlay failures in integrated circuit designs 失效
    用于执行蒙特卡罗模拟以预测集成电路设计中的覆盖故障的方法

    公开(公告)号：US06892365B2

    公开(公告)日：2005-05-10

    申请号：US10249524

    申请日：2003-04-16

    申请人： James A. Culp ,  Mark A. Lavin ,  Robert T. Sayah

    发明人： James A. Culp ,  Mark A. Lavin ,  Robert T. Sayah

    IPC分类号： H01L21/027 ,  G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer comprises providing design configurations for circuit portions to be lithographically produced on one or more adjacent layers of a semiconductor wafer, and then predicting shape and alignment for each circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error. The method then determines dimension of overlap of the predicted shape and alignment of the circuit portions, and compares the determined dimension of overlap to a theoretical minimum to determine whether the predicted dimension of overlap fails. Using different process fluctuation values and misalignment error values, the steps are then iteratively repeated on the provided design configurations to determine whether the predicted dimension of overlap fails, and a report is made of the measure of failures.

    摘要翻译： 预测半导体晶片的相邻的，光刻制造的层上的电路配置的覆盖失效的方法包括提供在半导体晶片的一个或多个相邻层上光刻制造的电路部分的设计配置，然后预测每个电路的形状和对准 每个相邻层上的部分使用用于过程波动或未对准误差的一个或多个预定值。 然后，该方法确定预测形状和电路部分的对准的重叠的尺寸，并将确定的重叠尺寸与理论最小值进行比较，以确定重叠的预测尺寸是否失败。 使用不同的过程波动值和未对准误差值，然后对提供的设计配置迭代重复这些步骤，以确定重叠的预测维度是否失败，并报告故障的测量。