利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

62 条记录 (耗时 0.044 秒)

    Object placement aid
    6.
    发明授权
    Object placement aid 失效
    对象放置辅助

    公开(公告)号：US5535134A

    公开(公告)日：1996-07-09

    申请号：US253898

    申请日：1994-06-03

    申请人： John M. Cohn ,  Fook-Luen Heng

    发明人： John M. Cohn ,  Fook-Luen Heng

    IPC分类号： H01L21/82 ,  G06F17/50

    CPC分类号： G06F17/509 ,  G06F17/5068 ,  G06F2217/06 ,  Y10S706/921

    摘要： An existing layout is modified to ensure compliance with design rules and any user-defined rules by deriving a horizontal constraint model and a vertical constraint model. For each of the vertical and horizontal orientations in turn, violations of the rules are identified. For each orientation in turn, the violations are removed in such a way that objects in the layout are moved the least amount necessary. A given object may also be inserted into an existing layout in such a way that perturbation of objects in the existing layout is minimized by exploring solutions allowing for object merger and non-merger solutions and choosing the best one based on predetermined criteria. Given a group of objects, a layout may also be created in such a way that successive objects are placed to minimize movement of objects already placed. Placement of an object in an existing layout may also be improved by removing the object and inserting it as if it were a new object a number of times until no further improvement is noted in its placement.

    摘要翻译： 修改现有布局以通过导出水平约束模型和垂直约束模型来确保符合设计规则和任何用户定义的规则。 依次对每个垂直和水平方向，都会识别违反规则的行为。 对于每个方向，依次删除违规行为，使布局中的对象移动到最少的必要数量。 给定对象也可以插入到现有布局中，使得通过探索允许对象合并和非合并解决方案并基于预定标准选择最佳对象的解决方案来最小化现有布局中的对象的扰动。 给定一组对象，也可以以这样的方式创建布局，使得连续的对象被放置以使已经放置的对象的移动最小化。 现有布局中的对象的放置也可以通过移除对象并将其插入多个对象来进行改进，直到在其布局中没有进一步改进。

    Pattern-matching for transistor level netlists
    7.
    发明授权
    Pattern-matching for transistor level netlists 失效
    晶体管级网表的模式匹配

    公开(公告)号：US06473881B1

    公开(公告)日：2002-10-29

    申请号：US09702313

    申请日：2000-10-31

    申请人： Valerie D. Lehner ,  John M. Cohn ,  Ulrich A. Finkler

    发明人： Valerie D. Lehner ,  John M. Cohn ,  Ulrich A. Finkler

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068

    摘要： A single pattern-matching algorithm which allows both exact and inexact pattern-matching so that transistor-level design automation tools can reliably perform timing analysis, electrical rules checking, noise analysis, test pattern generation, formal design verification, and the like prior to manufacturing custom logic. The user (circuit designer) specifies which of each of the pattern external nets may be matched inexactly (attached to Vdd, attached to GND, and shorted to other external nets), with the remainder of the pattern external net connections being matched using exact isomorphism constraints. The method described herein achieves a substantial reduction in the number of patterns which circuit designers must generate, and altogether eliminates the need for an exponential number of patterns by providing an inexact pattern matcher to circuit designers. It further provides rooted sub-graph isomorphism so that a user can query whether a particular pattern is embedded at a particular location in the main circuit design, utilizing inexact sub-graph isomorphism

    摘要翻译： 单一模式匹配算法，允许精确和不精确的模式匹配，以便晶体管级设计自动化工具可以在制造之前可靠地执行时序分析，电气规则检查，噪声分析，测试模式生成，正式设计验证等 定制逻辑。 用户（电路设计者）指定每个模式外部网络中的哪一个可以精确匹配（附加到Vdd，连接到GND，并与其他外部网络短接），其余模式外部网络连接使用精确同构 约束。 本文描述的方法实现了电路设计者必须生成的图案数量的显着减少，并且通过向电路设计者提供不精确的图案匹配器，完全不需要指数数目的图案。 它还提供了根系的子图同构，使得用户可以在主电路设计中的特定位置查询特定模式是否被嵌入，利用不精确的子图同构

    Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning
    8.
    发明授权
    Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning 有权
    设计子集，特征分析和产量学习的先验设计方法

    公开(公告)号：US07895545B2

    公开(公告)日：2011-02-22

    申请号：US12103217

    申请日：2008-04-15

    申请人： John M. Cohn ,  Leah M. Pastel ,  Gustavo E. Tellez

    发明人： John M. Cohn ,  Leah M. Pastel ,  Gustavo E. Tellez

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.

    摘要翻译： 一种用于设计子集，特征分析和产量学习的芯片设计方法。 该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。 该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

    System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA
    9.
    发明授权
    System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA 失效
    使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法

    公开(公告)号：US07644327B2

    公开(公告)日：2010-01-05

    申请号：US12049166

    申请日：2008-03-14

    申请人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    发明人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318519 ,  G01R31/318558 ,  G06F11/261 ,  H03K19/00392

    摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic unction, such that logic EC is provided within the embedded FPGA structure of the IC chip.

    摘要翻译： 一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。 该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。 如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。 识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。 识别有缺陷逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑逻辑的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

    Method of adding fabrication monitors to integrated circuit chips
    10.
    发明授权
    Method of adding fabrication monitors to integrated circuit chips 失效
    将制造监控器添加到集成电路芯片的方法

    公开(公告)号：US07620931B2

    公开(公告)日：2009-11-17

    申请号：US11859890

    申请日：2007-09-24

    申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

    发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

    IPC分类号： G06F17/50

    CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

    摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。