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    CA RESISTANCE VARIABILITY PREDICTION METHODOLOGY
    1.
    发明申请
    CA RESISTANCE VARIABILITY PREDICTION METHODOLOGY 有权
    CA抗性变异性预测方法

    公开(公告)号：US20090171644A1

    公开(公告)日：2009-07-02

    申请号：US11968458

    申请日：2008-01-02

    申请人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    发明人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.

    摘要翻译： 一种用于获得电子电路中CA电阻改进预测的方法，特别是改进的CA电阻模型，适用于捕获大于预期的“超出规范”状态。 在一个实施例中，实现了一种新颖的分层方案，其编码为电路设计者提供了相当好的设计选项，用于处理大的CA变异性，如通过设计手册所看到的。 开发用于建模CA可变电阻现象影响的工具为开发人员提供了一种电阻模型，如常规已知的，使用新的CA模型Basis进行修改，包括新颖的CA内在电阻模型，以及新颖的CA布局分层模型。

    CA resistance variability prediction methodology
    2.
    发明授权
    CA resistance variability prediction methodology 有权
    CA抗性变异性预测方法

    公开(公告)号：US07831941B2

    公开(公告)日：2010-11-09

    申请号：US11968458

    申请日：2008-01-02

    申请人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    发明人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.

    摘要翻译： 一种用于获得电子电路中CA电阻改进预测的方法，特别是改进的CA电阻模型，适用于捕获大于预期的“超出规范”状态。 在一个实施例中，实现了一种新颖的分层方案，其编码为电路设计者提供了相当好的设计选项，用于处理大的CA变异性，如通过设计手册所看到的。 开发用于建模CA可变电阻现象影响的工具为开发人员提供了一种电阻模型，如常规已知的，使用新的CA模型Basis进行修改，包括新颖的CA内在电阻模型，以及新颖的CA布局分层模型。

    METHOD OF INTEGRATED CIRCUIT CHIP FABRICATION AND PROGRAM PRODUCT THEREFOR
    8.
    发明申请
    METHOD OF INTEGRATED CIRCUIT CHIP FABRICATION AND PROGRAM PRODUCT THEREFOR 有权
    集成电路芯片制造方法及其程序产品

    公开(公告)号：US20100318956A1

    公开(公告)日：2010-12-16

    申请号：US12482504

    申请日：2009-06-11

    申请人： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien ,  Rama N. Singh

    发明人： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien ,  Rama N. Singh

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.

    摘要翻译： 一种用于集成电路（IC）芯片制造，物理设计系统及其程序产品的物理设计方法。 设计形状被分段为光学邻近校正（OPC）的段，并确定段的谐波平均值。 根据形状确定电气意图，并为段确定谐波平均值。 可以基于使用谐波平均成本函数测量的移动段的对谐波平均值的影响来移动段。 最后分段形状传递给OPC。

    Optimizing integrated circuit chip designs for optical proximity correction
    9.
    发明授权
    Optimizing integrated circuit chip designs for optical proximity correction 有权
    优化用于光学邻近校正的集成电路芯片设计

    公开(公告)号：US08122387B2

    公开(公告)日：2012-02-21

    申请号：US12482504

    申请日：2009-06-11

    申请人： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien, legal representative ,  Rama N. Singh

    发明人： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Rama N. Singh

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.

    摘要翻译： 一种用于集成电路（IC）芯片制造，物理设计系统及其程序产品的物理设计方法。 设计形状被分段为光学邻近校正（OPC）的段，并确定段的谐波平均值。 根据形状确定电气意图，并为段确定谐波平均值。 可以基于使用谐波平均成本函数测量的移动段的对谐波平均值的影响来移动段。 最后分段形状传递给OPC。

    Analyzing A Patterning Process Using A Model Of Yield
    10.
    发明申请
    Analyzing A Patterning Process Using A Model Of Yield 失效
    使用产量模型分析模式化过程

    公开(公告)号：US20130185046A1

    公开(公告)日：2013-07-18

    申请号：US13613061

    申请日：2012-09-13

    申请人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E. Rosenbluth ,  Rama N. Singh ,  Kehan Tian

    发明人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E. Rosenbluth ,  Rama N. Singh ,  Kehan Tian

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/10

    摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

    摘要翻译： 提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。 使用电路产量结果，确定至少模拟装置形状的高级特征。 基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到 满足至少一个第一预定标准。 构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。 使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。