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    Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained
    32.
    发明授权
    Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained 有权
    用于制造包括高压MOS晶体管的电子器件的制造方法以及由此获得的电子器件

    公开(公告)号：US06501147B1

    公开(公告)日：2002-12-31

    申请号：US09713144

    申请日：2000-11-14

    申请人： Bruno Vajana ,  Matteo Patelmo

    发明人： Bruno Vajana ,  Matteo Patelmo

    IPC分类号： H01L2900

    CPC分类号： H01L27/11526 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

    摘要： A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions of a second conductivity type, arranged at the sides of the first gate region. At the same time, a dual-gate HV MOS transistor is formed, the source and drain regions of which are housed in a tub formed in the substrate and having the first conductivity type, but at a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell simultaneously in a second tub of the substrate of semiconductor material.

    摘要翻译： 一种用于制造具有在衬底的非注入区域中具有低倍增系数和高阈值的HV MOS晶体管的电子器件的方法，该区域具有与衬底相同的导电类型和相同的掺杂水平。 通过在非植入衬底区域上形成具有与非植入衬底区域相同的掺杂类型的半导体材料的第一栅极区域来获得晶体管; 以及在所述非植入衬底区域内形成布置在所述第一栅极区域侧面的第二导电类型的第一源极和漏极区域。 同时，形成双栅极HV MOS晶体管，其源极和漏极区域被容纳在形成在衬底中的具有第一导电类型的桶中，但是具有比未植入衬底区域更高的浓度 。 此外，可以在半导体材料的基板的第二槽中同时形成非易失性存储单元。

    Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips
    33.
    发明授权
    Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips 失效
    具有叠加位线和短路金属条的非易失性半导体存储器件结构

    公开(公告)号：US06307229B2

    公开(公告)日：2001-10-23

    申请号：US09081881

    申请日：1998-05-19

    申请人： Nicola Zatelli ,  Federico Pio ,  Bruno Vajana

    发明人： Nicola Zatelli ,  Federico Pio ,  Bruno Vajana

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.

    摘要翻译： 一种具有半导体材料层中的存储单元矩阵的非易失性半导体存储器件结构。 存储单元位于矩阵的行和列的交点处。 每个存储单元包括连接到行中的一个的控制栅电极，连接到一列的第一电极和第二电极。 这些行包括在第一方向上彼此平行延伸的多晶硅条，并且所述列由在与第一方向正交的第二方向上彼此平行延伸的金属条形成。 短路金属带被耦合以使存储器单元的第二电极短路。 列和短路带分别形成在第一金属层和第二金属层之间，第二金属层与第二金属层叠在一起，并被电介质层电绝缘。

    Anti-deciphering contacts
    34.
    发明授权
    Anti-deciphering contacts 失效
    反解密触点

    公开(公告)号：US06528885B2

    公开(公告)日：2003-03-04

    申请号：US09968682

    申请日：2001-10-01

    申请人： Bruno Vajana ,  Matteo Patelmo

    发明人： Bruno Vajana ,  Matteo Patelmo

    IPC分类号： H01L2348

    CPC分类号： H01L27/0203 ,  G06K19/073 ,  H01L21/768 ,  H01L23/522 ,  H01L23/573 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making an integrated circuit that is resistant to an unauthorized duplication through reverse engineering includes forming a plurality of false contacts and/or false interconnection vias in the integrated circuit. These false contacts and/or false interconnection vias are connected as true contacts and true interconnection vias by lines patterned in a metallization layer deposited over an insulating dielectric layer or multilayer through which the true contacts and/or the true interconnection vias are formed. False contacts and false vias extend in the respective dielectric layers or multilayers to a depth insufficient to reach the active areas of a semiconductor substrate for false contacts, or to a depth insufficient to reach a layer of conductive material below the dielectric layers or multilayers for false interconnection vias.

    摘要翻译： 通过逆向工程制造抗未授权复制的集成电路的方法包括在集成电路中形成多个假触点和/或伪互连通孔。 这些假触点和/或伪互连通孔通过在沉积在绝缘介电层或多层上的金属化层中图案化的线连接为真实触点和真实的互连通孔，绝缘介电层或多层通过其形成真实的触点和/或真实的互连通孔。 假触点和假通孔在相应的电介质层或多层中延伸到不足以到达用于错误接触的半导体衬底的有源区的深度，或者到达不足以达到介电层或多层下方的导电材料层的深度为假 互连通孔

    Bipolar transistor compatible with CMOS processes
    36.
    发明授权
    Bipolar transistor compatible with CMOS processes 失效
    双极晶体管与CMOS工艺兼容

    公开(公告)号：US5793085A

    公开(公告)日：1998-08-11

    申请号：US481928

    申请日：1995-06-07

    申请人： Bruno Vajana ,  Emilio Ghio

    发明人： Bruno Vajana ,  Emilio Ghio

    IPC分类号： H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/76

    CPC分类号： H01L21/8249 ,  H01L21/8248 ,  H01L27/0623

    摘要： A bipolar transistor, comprising a collector region, a base region, and an emitter region, is a type which is compatible to CMOS processes leading to the formation, on a semiconductor substrate, of N-channel and P-channel MOS transistors having respective source and drain regions. In such bipolar transistor, the collector region is a substrate diffused pocket and the base region is formed within the diffused pocket simultaneously with the source and drain regions of the P-channel MOS transistors. Further, the emitter region is incorporated, in turn, to the base region simultaneously with the source and drain regions of the N-channel MOS transistors.

    摘要翻译： 包括集电极区域，基极区域和发射极区域的双极晶体管是与CMOS工艺兼容的类型，其导致在半导体衬底上形成具有相应源极的N沟道和P沟道MOS晶体管 和漏区。 在这种双极性晶体管中，集电极区域是衬底扩散的阱，并且基底区域与P沟道MOS晶体管的源极和漏极区域同时形成在扩散的凹穴内。 此外，发射极区域又与N沟道MOS晶体管的源极和漏极区域同时并入基极区域。

    Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells
    37.
    发明授权
    Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells 失效
    用于制造组件以限制编程电压并且使用EEPROM存储器单元稳定结合在电气设备中的电压的工艺

    公开(公告)号：US5322803A

    公开(公告)日：1994-06-21

    申请号：US946797

    申请日：1992-09-18

    申请人： Paolo Cappelletti ,  Giuseppe Corda ,  Paolo Ghezzi ,  Carlo Riva ,  Bruno Vajana

    发明人： Paolo Cappelletti ,  Giuseppe Corda ,  Paolo Ghezzi ,  Carlo Riva ,  Bruno Vajana

    IPC分类号： G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/266

    CPC分类号： H01L29/66106 ,  H01L27/115 ,  H01L27/11517 ,  Y10S148/174 ,  Y10S438/983

    摘要： The manufacturing process comprises a first step of formation of an N type sink on a single-crystal silicon substrate, a second step of formation of an active area on the surface of said sink, a third step of implantation of N- dopant in a surface region of the sink inside said active area, a fourth step of growth of a layer of gate oxide over said region with N- dopant, a fifth step of N+ implantation inside said N- region, a sixth step of P+ implantation in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

    摘要翻译： 该制造方法包括在单晶硅衬底上形成N型吸收体的第一步骤，在所述吸收体的表面上形成有源区的第二步骤，在表面上注入N掺杂剂的第三步骤 在所述有源区域内的宿的区域，在所述区域上用N-掺杂剂生长栅极氧化物层的第四步骤，在所述N-区域内N +注入的第五步骤，P +植入在横向位移中的第六步骤 相对于所述N +区域的位置，以及形成所述N +和P +区域的外部触点的第七步骤。 因此，获得了具有截止电压的齐纳二极管限幅器，该截止电压随着时间而稳定，并且不依赖于温度，并且不需要相对于完成EEPROM存储器单元通常所需的那些处理步骤。

    Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication
    38.
    发明授权
    Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication 有权

    公开(公告)号：US06614080B2

    公开(公告)日：2003-09-02

    申请号：US10056564

    申请日：2001-10-26

    申请人： Bruno Vajana ,  Matteo Patelmo

    发明人： Bruno Vajana ,  Matteo Patelmo

    IPC分类号： H01L27112

    CPC分类号： H01L27/11226 ,  H01L23/573 ,  H01L27/02 ,  H01L27/112 ,  Y10S257/922

    摘要： A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions. The plurality of second contacts define interconnection contacts by further extending through the first dielectric layer for contacting the second regions for memory cells programmed in a conductive state, and false interconnection contacts by not extending through the first dielectric layer for contacting the second regions for memory cells programmed in a non-conductive state.

    High-voltage N-channel MOS transistor and associated manufacturing process
    39.
    发明授权
    High-voltage N-channel MOS transistor and associated manufacturing process 失效
    高压N沟道MOS晶体管及相关制造工艺

    公开(公告)号：US5850360A

    公开(公告)日：1998-12-15

    申请号：US607779

    申请日：1996-02-27

    申请人： Bruno Vajana ,  Livio Baldi

    发明人： Bruno Vajana ,  Livio Baldi

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  G11C11/34

    CPC分类号： H01L21/823878 ,  H01L27/0928

    摘要： A CMOS device and process are disclosed in which two types of N-channel MOS transistors are provided, one being formed in a P-well and one being formed outside the P-well where the relatively low doping concentration of P-type substrate serves as a channel defining region. This second type N-channel transistor an support higher junction voltages due to the lower p-type doping concentration than is possible for the first type N-channel transistor formed in the higher doping concentration P-well. A mask is provided to prevent boron doping in the substrate at the site of the high voltage transistor during the implantation step which defines the P-well.

    摘要翻译： 公开了一种CMOS器件和工艺，其中提供两种类型的N沟道MOS晶体管，一种形成在P阱中，一种形成在P阱外部，其中P型衬底的相对低的掺杂浓度用作 一个通道定义区域。 该第二类型N沟道晶体管由于较低掺杂浓度的P型掺杂浓度而支持较高的结电压，这对于在较高掺杂浓度P阱中形成的第一型N沟道晶体管是可能的。 提供掩模以在限定P阱的注入步骤期间防止在高压晶体管的位置处的衬底中的硼掺杂。