公开(公告)号：US5322803A

公开(公告)日：1994-06-21

申请号：US946797

申请日：1992-09-18

申请人： Paolo Cappelletti ,  Giuseppe Corda ,  Paolo Ghezzi ,  Carlo Riva ,  Bruno Vajana

发明人： Paolo Cappelletti ,  Giuseppe Corda ,  Paolo Ghezzi ,  Carlo Riva ,  Bruno Vajana

IPC分类号： G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/266

CPC分类号： H01L29/66106 ,  H01L27/115 ,  H01L27/11517 ,  Y10S148/174 ,  Y10S438/983

摘要： The manufacturing process comprises a first step of formation of an N type sink on a single-crystal silicon substrate, a second step of formation of an active area on the surface of said sink, a third step of implantation of N- dopant in a surface region of the sink inside said active area, a fourth step of growth of a layer of gate oxide over said region with N- dopant, a fifth step of N+ implantation inside said N- region, a sixth step of P+ implantation in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

摘要翻译： 该制造方法包括在单晶硅衬底上形成N型吸收体的第一步骤，在所述吸收体的表面上形成有源区的第二步骤，在表面上注入N掺杂剂的第三步骤 在所述有源区域内的宿的区域，在所述区域上用N-掺杂剂生长栅极氧化物层的第四步骤，在所述N-区域内N +注入的第五步骤，P +植入在横向位移中的第六步骤 相对于所述N +区域的位置，以及形成所述N +和P +区域的外部触点的第七步骤。 因此，获得了具有截止电压的齐纳二极管限幅器，该截止电压随着时间而稳定，并且不依赖于温度，并且不需要相对于完成EEPROM存储器单元通常所需的那些处理步骤。

公开(公告)号：US5393684A

公开(公告)日：1995-02-28

申请号：US988474

申请日：1992-12-10

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/266

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7883 ,  H01L27/115 ,  Y10S438/911 ,  Y10S438/981

摘要： A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

摘要翻译： 一种用于在电可擦除和可编程只读存储器单元中形成薄氧化物部分的方法，包括使用增强的氧化效应和重掺杂的横向扩散，以获得其尺寸小于光刻方法的分辨率的隧道部分 用过的。

公开(公告)号：USRE37308E1

公开(公告)日：2001-08-07

申请号：US08376300

申请日：1995-01-23

申请人： Paolo G. Cappelletti ,  Giuseppe Corda ,  Carlo Riva

发明人： Paolo G. Cappelletti ,  Giuseppe Corda ,  Carlo Riva

IPC分类号： H01L29788

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n+ diffusion which is closed and isolated from those of the other cells of the same memory.

摘要翻译： 电池由选择晶体管，检测晶体管和隧道冷凝器形成。 检测晶体管具有形成有n +扩散的其自己的控制栅极，其与相同存储器的其它单元的封闭隔离。

公开(公告)号：US5132239A

公开(公告)日：1992-07-21

申请号：US574677

申请日：1990-08-30

申请人： Paolo Ghezzi ,  Carlo Riva ,  Grazia Valentini

发明人： Paolo Ghezzi ,  Carlo Riva ,  Grazia Valentini

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L21/31662 ,  H01L27/115 ,  H01L29/7883 ,  H01L21/28167 ,  H01L21/28211

摘要： The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor, sensing transistor having a floating gate, control gate with a capacitive coupling to the floating gate and a tunnel area with thin oxide, comprises a first step involving the definition of active areas free of field oxide, a second step involving an ionic implantation at a coupling area between the control gate and the floating gate, a third step involving the creation of gate oxide at the active areas, a fourth step involving an additional ionic implantation at said coupling area between the control gate and the floating gate and at said tunnel area, a fifth step involving the removal of the gate oxide superimposed over said areas, a sixth step involving the differentiated growth of coupling oxide and tunnel oxide at said coupling areas and tunnel areas and a seventh step involving the deposition of a layer of polysilicon constituting the floating gate.

公开(公告)号：US5553017A

公开(公告)日：1996-09-03

申请号：US310836

申请日：1994-09-22

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

摘要翻译： 一种用于制造具有单个多晶硅级别的电可擦除和可编程只读存储器单元的方法，包括使用氧化硅牺牲层在有源区上产生高厚度氧化硅层。 为了提高可靠性，保护电池的有源区域免受重的源极和漏极注入。

公开(公告)号：US5527728A

公开(公告)日：1996-06-18

申请号：US329309

申请日：1994-10-26

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7883 ,  H01L27/115 ,  Y10S438/911 ,  Y10S438/981

摘要： A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

摘要翻译： 一种用于在电可擦除和可编程只读存储器单元中形成薄氧化物部分的方法，包括使用增强的氧化效应和重掺杂的横向扩散，以获得其尺寸小于光刻方法的分辨率的隧道部分 用过的。

公开(公告)号：US4935790A

公开(公告)日：1990-06-19

申请号：US136652

申请日：1987-12-22

申请人： Paolo G. Cappelletti ,  Giuseppe Corda ,  Carlo Riva

发明人： Paolo G. Cappelletti ,  Giuseppe Corda ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n.sup.+ diffusion which is closed and isolated from those of the other cells of the same memory.

公开(公告)号：US5367483A

公开(公告)日：1994-11-22

申请号：US983799

申请日：1992-11-24

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  H01L21/70

CPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

摘要翻译： 一种用于制造具有单个多晶硅级别的电可擦除和可编程只读存储器单元的方法，包括使用氧化硅牺牲层在有源区上产生高厚度氧化硅层。 为了提高可靠性，保护电池的有源区域免受重的源极和漏极注入。

公开(公告)号：US06278163B1

公开(公告)日：2001-08-21

申请号：US09224939

申请日：1998-12-31

申请人： Federico Pio ,  Carlo Riva

发明人： Federico Pio ,  Carlo Riva

IPC分类号： H01L31062

CPC分类号： H01L29/66575 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/7833

摘要： An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

摘要翻译： 集成在具有第一类型导电性的半导体衬底中的HV晶体管，包括在相应的漏极和源极区域之间包括的栅极区域，并且其中至少所述漏极区域被轻掺杂第二类型的导电性。 漏极区域包括具有第二类型导电性的接触区域，但是其重新掺杂，接触焊盘从该区域延伸。

公开(公告)号：US6057591A

公开(公告)日：2000-05-02

申请号：US14437

申请日：1998-01-27

申请人： Camilla Calegari ,  Anna Carrara ,  Lorenzo Fratin ,  Carlo Riva

发明人： Camilla Calegari ,  Anna Carrara ,  Lorenzo Fratin ,  Carlo Riva

IPC分类号： H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L23/29

CPC分类号： H01L23/564 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/958

摘要： A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

摘要翻译： 一种用于形成器件边缘形态结构的方法，用于在半导体材料的衬底的主表面周围保护和密封电子电路。 电子电路是要求在至少一个电介质多层的主表面上形成的类型的电路。 电介质多层包括一层无定形平面化材料，其具有连续部分，该连续部分在形状结构中具有更内部的第一区域和更外部的第二区域的两个连续区域之间延伸。 设备边缘形态结构包括在基底中的形状结构的更内部的第一区域的主表面侧的开口，其中存在电介质多层的连续部分的区域。