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170 条记录 (耗时 0.058 秒)

    Self-aligned silicidation for replacement gate process
    34.
    发明授权
    Self-aligned silicidation for replacement gate process 有权
    用于替代浇口工艺的自对准硅化物

    公开(公告)号：US08779529B2

    公开(公告)日：2014-07-15

    申请号：US13692369

    申请日：2012-12-03

    申请人： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

    发明人： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

    IPC分类号： H01L21/02

    CPC分类号： H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

    摘要： A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

    摘要翻译： 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

    Method to dynamically tune precision resistance
    35.
    发明授权
    Method to dynamically tune precision resistance 有权
    动态调整精度电阻的方法

    公开(公告)号：US08709882B2

    公开(公告)日：2014-04-29

    申请号：US12683759

    申请日：2010-01-07

    申请人： Steven R. Soss ,  Andreas Knorr

    发明人： Steven R. Soss ,  Andreas Knorr

    IPC分类号： H01L21/00

    CPC分类号： H01L28/20

    摘要： A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.

    摘要翻译： 形成具有可控电阻的精密电阻器，以补偿随温度发生的变化。 一个实施例包括形成在衬底上具有宽度和长度的电阻半导体元件，跨越电阻半导体元件的宽度图形化导电线，但与之电隔离，并且在电气半导体元件下方形成耗尽沟道 导线来控制电阻半导体元件的电阻值。 该设计能够动态调节电阻，从而提高电阻器的可靠性或允许最终封装期间的电阻修改。

    Providing conversion of a planar design to a FinFET design
    38.
    发明授权
    Providing conversion of a planar design to a FinFET design 有权
    提供平面设计到FinFET设计的转换

    公开(公告)号：US08533651B1

    公开(公告)日：2013-09-10

    申请号：US13552313

    申请日：2012-07-18

    申请人： Soon Yoeng Tan ,  Angeline Ho ,  Hendry Renaldo ,  Andreas Knorr ,  Scott Johnson

    发明人： Soon Yoeng Tan ,  Angeline Ho ,  Hendry Renaldo ,  Andreas Knorr ,  Scott Johnson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5077

    摘要： An approach for providing conversion of a planar design to a FinFET design is disclosed. Embodiments include: receiving a planar design having a plurality of diffusion regions; overlapping a plurality of parallel fin mandrels with a plurality of evenly-spaced parallel lines of a grid; snapping the diffusion regions to the grid based on the parallel lines; and generating a FinFET design based on the overlapping and the snapping. Embodiments include the parallel lines and the parallel fin mandrels being perpendicular to a poly orientation associated with the planar design, and determining a spacing length between the parallel lines; determining a plurality of edges of the diffusion regions that are parallel to the poly orientation; and cropping the diffusion regions until each of the edges has a length that is a multiple of the spacing length.

    摘要翻译： 公开了一种将平面设计转换成FinFET设计的方法。 实施例包括：接收具有多个扩散区域的平面设计; 将多个平行翅片心轴与网格的多个均匀间隔平行的线重叠; 基于平行线将扩散区捕捉到栅格; 并基于重叠和捕捉产生FinFET设计。 实施例包括垂直于与平面设计相关联的聚取向并且确定平行线之间的间隔长度的平行线和平行翅片心轴; 确定所述扩散区域的平行于所述聚取向的多个边缘; 并且切割扩散区域，直到每个边缘具有为间隔长度的倍数的长度。