公开(公告)号：US4879690A

公开(公告)日：1989-11-07

申请号：US231063

申请日：1988-08-11

申请人： Kenji Anami ,  Katsuki Ichinose ,  Tomohisa Wada

发明人： Kenji Anami ,  Katsuki Ichinose ,  Tomohisa Wada

IPC分类号： G11C5/00 ,  G11C11/412

CPC分类号： G11C11/4125 ,  G11C5/005

摘要： A storage node in each of memory cells in a static RAM is connected to a bit line through an accessing MOSFET. The accessing MOSFET has its gate connected to a word line. A word line driver comprising a level shifting N channel MOSFET and a CMOS inverter is connected to the word line. At the time of selecting the word line, a potential which is lower, by a threshold voltage of the MOSFET, than a power-supply potential is applied to the word line. Thus, a sub-threshold current flowing in the MOSFET connected between the storage node for storing data at a high level and the bit line to which data of a high level is read out becomes substantially small, so that a potential of the storage node for storing data of a high level is not lowered.

摘要翻译： 静态RAM中每个存储单元中的存储节点通过访问MOSFET连接到位线。 存取MOSFET的栅极连接到字线。 包括电平移位N沟道MOSFET和CMOS反相器的字线驱动器连接到字线。 在选择字线时，对字线施加低于MOSFET的阈值电压的电位低于电源电位的电位。 因此，在连接在用于存储高电平的数据的存储节点和读出高电平的数据的位线之间的MOSFET中流动的子阈值电流变得基本上小，从而存储节点的电位 存储高电平的数据不降低。

公开(公告)号：US4751683A

公开(公告)日：1988-06-14

申请号：US771709

申请日：1985-09-03

申请人： Tomohisa Wada ,  Hirofumi Shinohara

发明人： Tomohisa Wada ,  Hirofumi Shinohara

IPC分类号： G11C11/34 ,  G11C8/08 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C8/18

摘要： A semiconductor memory device in accordance with the present invention operates in response to an address transition detection (ATD) signal for detecting a change in an x address as well as to a write enable signal WE to make the signal level on a selected word line vary according to the read mode and the write mode, whereby dissipation of electric power can be reduced.

摘要翻译： 根据本发明的半导体存储器件响应于用于检测x地址变化的地址转换检测（ATD）信号以及写入使能信号和上拉沿W而在所选择的字线上产生信号电平 根据读取模式和写入模式而变化，从而可以减少功率耗散。

公开(公告)号：US06519187B2

公开(公告)日：2003-02-11

申请号：US09960973

申请日：2001-09-25

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C710

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00 ,  G11C2207/2218 ,  G11C2207/2245

摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by a latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculators, work stations and personal computers can be improved.

摘要翻译： 与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。 保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。 在不从存储单元阵列读出数据的期间，由锁存电路取入写入数据。 比较器比较保持的内部地址信号和用于读取数据的内部地址信号。 如果在它们之间找到匹配，则多路复用器从锁存电路输出数据以进行外部输出。 因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓冲存储器的高速操作以及诸如超级计算机等各种级别的计算机的速度性能， 大型计算器，工作站和个人计算机可以改进。

公开(公告)号：US5859806A

公开(公告)日：1999-01-12

申请号：US901938

申请日：1997-07-29

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H01L27/10 ,  G11C7/02

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C2207/2245

摘要： A computer includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal, and being operable to output a data output fixing signal attaining a predetermined level in response to output of the data, and a processing device operable to apply the address signal to the storage device, take in the data from the storage device in response to the fact that the data output fixing signal attains the predetermined level, and perform processing in accordance with the data. The storage device and the processing device may be formed on a single chip. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapse of a maximum access time determined in a specification prescribed taking the worst conditions into consideration.

摘要翻译： 计算机包括具有多个存储器单元的存储装置，可操作以输出存储在对应于地址信号的存储单元中的数据，并且可操作以响应于数据的输出而输出达到预定电平的数据输出固定信号 以及可操作以将地址信号施加到存储装置的处理装置，响应于数据输出固定信号达到预定电平的事实从存储装置接收数据，并根据该数据进行处理。 存储装置和处理装置可以形成在单个芯片上。 每当输出数据输出固定信号时，处理装置可以接收和处理数据。 当存储装置在比最差条件更好的条件下运行时，可以在经过考虑到最差条件规定的规格中确定的最大访问时间之前执行数据处理。

公开(公告)号：US5808930A

公开(公告)日：1998-09-15

申请号：US676740

申请日：1996-07-08

申请人： Tomohisa Wada ,  Motomu Ukita ,  Toshihiko Hirose ,  Eiichi Ishikawa

发明人： Tomohisa Wada ,  Motomu Ukita ,  Toshihiko Hirose ,  Eiichi Ishikawa

IPC分类号： H01L27/11 ,  G11C5/14 ,  G11C7/10 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8244 ,  G11C5/06

CPC分类号： G11C11/4097 ,  G11C5/14 ,  G11C7/10 ,  G11C7/18

摘要： In a line configuration of each memory cell array employed in a semiconductor memory device, a pair of bit line signal input/output lines or a pair of input/output data lines for transmitting complementary signals are disposed on both sides of and adjacent the global word line so as to cancel the influence of the global word line. By these configurations, the number of shielded lines may be reduced and the width of each line and the interval between the lines are arrayed for preventing the respective lines from breaking or being short-circuited.

摘要翻译： 在半导体存储器件中使用的每个存储单元阵列的线路配置中，一对位线信号输入/输出线或用于传输互补信号的一对输入/输出数据线布置在全局字的两侧 以消除全球字线的影响。 通过这些配置，可以减少屏蔽线的数量，并且排列每条线的宽度和线之间的间隔，以防止各条线断裂或短路。

公开(公告)号：US5752270A

公开(公告)日：1998-05-12

申请号：US846206

申请日：1997-04-28

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G06F13/16 ,  G06F12/00

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00 ,  G11C2207/2218 ,  G11C2207/2245

摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

摘要翻译： 与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。 保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。 在从存储单元阵列未读出数据的期间，写入数据被锁存电路取入并保持。 比较器比较保持的内部地址信号和用于读取数据的内部地址信号。 如果它们之间发现匹配，则多路复用器从锁存电路输出数据以进行外部输出。 因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓存存储器的高速操作，并且实现诸如超级计算机， 大型计算器，工作站和个人计算机可以改进。

公开(公告)号：US5699308A

公开(公告)日：1997-12-16

申请号：US686626

申请日：1996-07-24

申请人： Tomohisa Wada ,  Motomu Ukita

发明人： Tomohisa Wada ,  Motomu Ukita

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/407 ,  G11C29/00 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  G11C7/00 ,  G11C5/06

CPC分类号： G11C29/804 ,  G11C29/80 ,  G11C29/848 ,  G11C7/18 ,  H01L27/11

摘要： In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.

摘要翻译： 在包括字线，位线和布置在字线和位线之间的交叉点处的多个存储单元的半导体存储单元阵列中，位线被分组为奇数和偶数编号组。 移位冗余电路被布置在每组奇数或偶数位线与读出放大器和写入电路之间，用于将有缺陷的存储器单元移位到冗余存储器单元。

公开(公告)号：US5471427A

公开(公告)日：1995-11-28

申请号：US262755

申请日：1994-06-20

申请人： Shuji Murakami ,  Tomohisa Wada ,  Kenji Anami

发明人： Shuji Murakami ,  Tomohisa Wada ,  Kenji Anami

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/848

摘要： A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and nor program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.

摘要翻译： 在行或列解码器和存储单元阵列之间提供用于修复有缺陷的存储单元的电路。 当解码器具有n条输出线时，存储单元阵列至少包括（N + 1）行或列线，其中n是整数。 修复电路包括用于将解码器的输出线连接到行或列线的连接电路，以及用于限定连接电路的连接的电路。 连接电路包括n个开关元件，每个开关元件可操作以将解码器的一个输出线连接到至少两个行或列线。 定义电路定义每个开关元件的连接路径，使得解码器的输出线与连续有缺陷的存储器单元的行或列线排除在连续定位的行或列之间一一对应。 定义电路包括设置在工作电压源和接地线之间的一系列激光可编程保险丝元件。 由于没有备用解码器和编程电路，修复电路占用了芯片的减少面积，并且由于要被熔断的熔丝元件的数量减少，所以它进行可靠且快速的存储器修复。

公开(公告)号：US5379258A

公开(公告)日：1995-01-03

申请号：US828254

申请日：1992-01-30

申请人： Shuji Murakami ,  Tomohisa Wada ,  Kenji Anami

发明人： Shuji Murakami ,  Tomohisa Wada ,  Kenji Anami

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/848 ,  G11C29/70

摘要： A circuit for repairing a defective memory cell between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and no program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.

摘要翻译： 一种用于修复行或列解码器和存储单元阵列之间的有缺陷的存储单元的电路。 当解码器具有n条输出线时，存储单元阵列至少包括（N + 1）行或列线，其中n是整数。 修复电路包括用于将解码器的输出线连接到行或列线的连接电路和用于限定连接电路的连接的电路。 连接电路包括n个开关元件，每个开关元件可操作以将解码器的一个输出线连接到至少两个行或列线。 定义电路定义每个开关元件的连接路径，使得解码器的输出线与连续有缺陷的存储器单元的行或列线排除在连续定位的行或列之间一一对应。 定义电路包括设置在工作电压源和接地线之间的一系列激光可编程保险丝元件。 由于没有备用解码器和编程电路，修复电路占用了芯片的减少面积，并且由于要被熔断的熔丝元件的数量减少，所以其执行可靠且快速的存储器修复。

公开(公告)号：US5307307A

公开(公告)日：1994-04-26

申请号：US495037

申请日：1990-03-16

申请人： Tomohisa Wada ,  Katsuki Ichinose

发明人： Tomohisa Wada ,  Katsuki Ichinose

IPC分类号： G11C11/401 ,  G11C7/12 ,  G11C7/18 ,  G11C11/41 ,  G11C13/00 ,  G11C11/00

CPC分类号： G11C7/12 ,  G11C7/18

摘要： A semiconductor memory device includes a memory cell array composed of a plurality of memory cells. The memory cell array includes a plurality of word lines interconnecting the memory cells in the row direction and a plurality of bit line pairs interconnecting the memory cells in the column direction. One end of each bit line pair is connected to a clamping circuit, while the other end of each bit line pair is connected via a column select gate to a read/write circuit. Each bit line pair is bent about centrally in the two-dimensional form of a letter U and the clamping circuit and the column select gate are disposed alternately on one same straight line.

摘要翻译： 半导体存储器件包括由多个存储单元组成的存储单元阵列。 存储单元阵列包括将行方向上的存储单元互连的多个字线和在列方向上互连存储单元的多个位线对。 每个位线对的一端连接到钳位电路，而每个位线对的另一端通过列选择栅极连接到读/写电路。 每个位线对以字母U的二维形式围绕中心弯曲，钳位电路和列选择栅极交替地设置在同一条直线上。