公开(公告)号：US10008273B2

公开(公告)日：2018-06-26

申请号：US15181346

申请日：2016-06-13

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Gerrit Jan Hemink ,  Mohan Dunga ,  Bijesh Rajamohanan ,  Changyuan Chen

IPC: G11C16/28 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C29/02 ,  G11C7/12 ,  G11C29/12

CPC classification number: G11C16/28 ,  G06F11/1068 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/1204

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.

公开(公告)号：US09711231B1

公开(公告)日：2017-07-18

申请号：US15191898

申请日：2016-06-24

Applicant: SanDisk Technologies LLC

Inventor： Chris Yip ,  Philip Reusswig ,  Nian Niles Yang ,  Grishma Shah ,  Abuzer Azo Dogan ,  Biswajit Ray ,  Mohan Dunga ,  Joanna Lai ,  Changyuan Chen

IPC: G11C16/26 ,  G11C16/28 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/28 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/32

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

公开(公告)号：US09704588B1

公开(公告)日：2017-07-11

申请号：US15069287

申请日：2016-03-14

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Mohan Dunga ,  Changyuan Chen

IPC: G11C16/06 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C7/06

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C7/062 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/344 ,  G11C2211/5621

Abstract: Reduced errors when sensing non-volatile memory are provided by applying a current spike or preconditioning current for a group of memory cells included a selected cell. During a sense operation, a preconditioning current can be passed through a group of non-volatile memory cells. The preconditioning current is provided prior to applying at least one reference voltage to a selected word line. The preconditioning current may simulate a cell current passing through the channel during a verification phase of programming. The preconditioning current can modify a channel resistance to approximate a state during verification to provide a more stable threshold voltage for the memory cells. Preconditioning currents may be applied selectively for select reference levels, select pages, and/or select operations. Selective application of preconditioning currents based on temperature is also provided.