公开(公告)号：US11482539B2

公开(公告)日：2022-10-25

申请号：US17082629

申请日：2020-10-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar

IPC: H01L25/18 ,  G11C16/14 ,  H01L27/11582 ,  H01L25/065 ,  H01L23/00 ,  H01L29/04 ,  H01L29/45 ,  H01L21/285 ,  H01L21/02 ,  H01L25/00 ,  H01L27/11556

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.

公开(公告)号：US11469241B2

公开(公告)日：2022-10-11

申请号：US16849664

申请日：2020-04-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Senaka Kanakamedala ,  Fei Zhou ,  Yao-Sheng Lee

IPC: H01L27/11556 ,  H01L29/423 ,  H01L23/538 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.

公开(公告)号：US11430736B2

公开(公告)日：2022-08-30

申请号：US17000934

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Yao-Sheng Lee

IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L27/11582

Abstract: A semiconductor structure includes first metal lines located above at least one semiconductor device, and a continuous metal organic framework (MOF) material layer including lower MOF portions that are located between neighboring pairs of first metal lines and an upper MOF matrix portion that continuously extends over the first metal lines and connected to each of the lower MOF portions.

公开(公告)号：US11377733B2

公开(公告)日：2022-07-05

申请号：US16987717

申请日：2020-08-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Yusuke Mukae ,  Naoki Takeguchi

IPC: C23C16/08 ,  C23C16/448 ,  C23C16/455 ,  C23C16/52 ,  C23C16/02

Abstract: A method of depositing tungsten over a substrate includes disposing the substrate into a vacuum enclosure of a tungsten deposition apparatus, performing a first tungsten deposition process that deposits a first tungsten layer over a physically exposed surface of the substrate by flowing a fluorine-containing tungsten precursor gas into the vacuum enclosure, performing an in-situ oxidation process by exposing the first tungsten layer to an oxidation agent gas while the substrate remains within the vacuum enclosure without breaking vacuum and forming a tungsten oxyfluoride gas which is pumped out of the vacuum enclosure, and performing a second tungsten deposition process that deposits a second tungsten layer on the first tungsten layer by flowing the fluorine-containing tungsten precursor gas into the vacuum enclosure in a second tungsten deposition process after the in-situ oxidation process.

公开(公告)号：US11374020B2

公开(公告)日：2022-06-28

申请号：US16887659

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Peter Rabkin ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/207 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US11309332B2

公开(公告)日：2022-04-19

申请号：US16568668

申请日：2019-09-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Seung-Yeul Yang ,  Fei Zhou

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11597 ,  H01L27/1159 ,  H01L27/11587

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.

公开(公告)号：US11282848B2

公开(公告)日：2022-03-22

申请号：US16876877

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli Zhang ,  Fei Zhou ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11539 ,  H01L27/11597 ,  H01L27/11524

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US11127728B2

公开(公告)日：2021-09-21

申请号：US16848137

申请日：2020-04-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Rahul Sharangpani

IPC: G11C5/04 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L23/48

Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.

公开(公告)号：US11063063B2

公开(公告)日：2021-07-13

申请号：US16710481

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Dong-il Moon ,  Raghuveer S. Makala ,  Peng Zhang ,  Wei Zhao ,  Ashish Baraskar

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/532 ,  H01L21/311 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L23/528 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US11024648B2

公开(公告)日：2021-06-01

申请号：US16743436

申请日：2020-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Yanli Zhang ,  Seung-Yeul Yang ,  Fei Zhou

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519

Abstract: A ferroelectric memory device includes a semiconductor channel, a gate electrode, and a ferroelectric memory element located between the semiconductor channel and the gate electrode. The ferroelectric memory element includes at least one ferroelectric material portion and at least one antiferroelectric material portion.