公开(公告)号：US20240420626A1

公开(公告)日：2024-12-19

申请号：US18701699

申请日：2022-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Susumu KAWASHIMA ,  Koji KUSUNOKI ,  Tomoaki ATSUMI

IPC: G09G3/32

Abstract: A display device whose change in chromaticity is small and grayscale controllability is high is provided. Light emission of the light-emitting device can be performed by PAM and PWM control (a pulse width control involving changes in amplitude), so that the amount of change in chromaticity can be reduced and the controllability on the low grayscale side can be increased. The display device includes a pulse-signal-generation portion and a light-emitting control portion in a pixel and is capable of charging a signal potential in the light-emitting control portion and then discharging the signal potential in accordance with a pulse signal generated in the pulse-signal-generation portion. Thus, the light-emitting device can emit light in a desired period with desired emission intensity.

公开(公告)号：US20240296881A1

公开(公告)日：2024-09-05

申请号：US18646415

申请日：2024-04-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Junpei SUGAO

IPC: G11C11/4094 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/12 ,  H01L29/786 ,  H10B10/00 ,  H10B41/70

CPC classification number: G11C11/4094 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696 ,  H10B10/12 ,  H10B41/70

Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

公开(公告)号：US20230369344A1

公开(公告)日：2023-11-16

申请号：US18140797

申请日：2023-04-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji KUSUNOKI ,  Susumu KAWASHIMA ,  Hideaki SHISHIDO ,  Tomoaki ATSUMI ,  Motoharu SAITO

IPC: H01L27/12 ,  G09G3/3233

CPC classification number: H01L27/1237 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2310/08

Abstract: A semiconductor device including a first transistor, a second transistor, and an insulating layer is provided. The first transistor includes a first semiconductor layer and a first conductive layer. The second transistor includes a second semiconductor layer and a second conductive layer. The insulating layer includes a first side surface over the first conductive layer and a second side surface over the second conductive layer. A gate insulating layer includes a portion facing the first side surface with the first semiconductor layer therebetween and a portion facing the second side surface with the second semiconductor layer therebetween. A gate electrode includes a portion facing the first side surface with the gate insulating layer and the first semiconductor layer therebetween and a portion facing the second side surface with the gate insulating layer and the second semiconductor layer therebetween. The first semiconductor layer is electrically connected to the second semiconductor layer.

公开(公告)号：US20230260556A1

公开(公告)日：2023-08-17

申请号：US18138196

申请日：2023-04-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/12 ,  H01L29/221 ,  H10B12/00

CPC classification number: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/1225 ,  H01L29/221 ,  H10B12/00

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

公开(公告)号：US20220093141A1

公开(公告)日：2022-03-24

申请号：US17540314

申请日：2021-12-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/12 ,  H01L29/221

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

公开(公告)号：US20210383881A1

公开(公告)日：2021-12-09

申请号：US17286538

申请日：2019-10-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Tomoaki ATSUMI ,  Shunpei YAMAZAKI

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/12

Abstract: A semiconductor device that writes data to, instead of a defective memory cell, another memory cell is provided. The semiconductor device includes a first circuit and a second circuit over the first circuit; the first circuit corresponds to a memory portion and includes a memory cell and a redundant memory cell; a second circuit corresponds to a control portion and includes a third circuit and a fourth circuit. The memory cell is electrically connected to the third circuit, the redundant memory cell is electrically connected to the third circuit, and the third circuit is electrically connected to the fourth circuit. The fourth circuit has a function of sending data to be written to the memory cell or the redundant memory cell to the third circuit, and the third circuit has a function of bringing the memory cell and the fourth circuit into a non-conduction state and the redundant memory cell and the fourth circuit into a conduction state to send the data to the redundant memory cell when the memory cell is a defective cell.

公开(公告)号：US20210242220A1

公开(公告)日：2021-08-05

申请号：US17236115

申请日：2021-04-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tomoaki ATSUMI ,  Yuta ENDO

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/04

Abstract: A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

公开(公告)号：US20210134847A1

公开(公告)日：2021-05-06

申请号：US16616707

申请日：2018-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: H01L27/12 ,  H01L27/108

Abstract: A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.

公开(公告)号：US20210012816A1

公开(公告)日：2021-01-14

申请号：US16764955

申请日：2018-11-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: G11C7/04 ,  G11C11/4074 ,  G11C5/14 ,  H01L27/108 ,  H01L27/12 ,  H01L29/221

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

公开(公告)号：US20200265887A1

公开(公告)日：2020-08-20

申请号：US16759013

申请日：2018-11-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Shuhei MAEDA

IPC: G11C11/4094 ,  H01L29/786 ,  H01L27/108

Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.