公开(公告)号：US20220199653A1

公开(公告)日：2022-06-23

申请号：US17611689

申请日：2020-05-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuto YAKUBO ,  Hitoshi KUNITAKE ,  Takayuki IKEDA

IPC: H01L27/12 ,  H03B5/12

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes an oscillation circuit including a first coil, a second coil, a first capacitor, a second capacitor, a first transistor, and a second transistor and a frequency correction circuit including a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a switching circuit. The switching circuit has a function of controlling a conduction state or a non-conduction state of the third transistor and the fourth transistor. The frequency correction circuit is provided above the oscillation circuit and has a function of adjusting an oscillation frequency of the oscillation circuit. The first transistor and the second transistor each include a semiconductor layer containing silicon in a channel formation region. The third transistor and the fourth transistor each include a semiconductor layer containing an oxide semiconductor in a channel formation region.

公开(公告)号：US20220180920A1

公开(公告)日：2022-06-09

申请号：US17439876

申请日：2020-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiya SAITO ,  Yuto YAKUBO ,  Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: G11C11/4097 ,  G11C11/4091 ,  H01L27/108 ,  H01L29/786

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.

公开(公告)号：US20220093600A1

公开(公告)日：2022-03-24

申请号：US17427934

申请日：2020-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Yuto YAKUBO ,  Seiya SAITO

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.

公开(公告)号：US20210376848A1

公开(公告)日：2021-12-02

申请号：US17282098

申请日：2019-10-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Yuto YAKUBO ,  Kiyoshi KATO ,  Seiya SAITO

IPC: H03M1/12 ,  G11C27/02 ,  G01D21/00

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit that retains a voltage corresponding to an output signal of an amplifier input to the sample-and-hold circuit, an analog-to-digital converter circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of switching and controlling a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is retained in the sample-and-hold circuit and a second control period in which a digital signal obtained by output of the voltage retained in the sample-and-hold circuit to the analog-to-digital converter circuit is output to the interface circuit. In the first control period, the analog-to-digital converter circuit is switched to stop output of the digital signal. The first control period is longer than the second control period.

公开(公告)号：US20150340076A1

公开(公告)日：2015-11-26

申请号：US14718143

申请日：2015-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Shuhei NAGATSUKA

IPC: G11C11/24 ,  H01L27/12 ,  H01L29/786 ,  G11C5/14 ,  H01L29/24

CPC classification number: G11C11/24 ,  G11C11/5621 ,  G11C11/565 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869

Abstract: A highly reliable storage device with small data deterioration is provided. The storage device includes a first circuit, a second circuit, a third circuit, and a memory cell. The first circuit has a function of detecting power-on. The second circuit has a function of specifying the address of the memory cell. The third circuit has a function of refreshing the memory cell at the address specified by the second circuit after the first circuit detects power-on. The memory cell preferably includes an oxide semiconductor transistor.

Abstract translation: 提供了具有小数据恶化的高度可靠的存储设备。 存储装置包括第一电路，第二电路，第三电路和存储单元。 第一电路具有检测上电功能。 第二电路具有指定存储单元的地址的功能。 第三电路具有在第一电路检测到上电之后刷新由第二电路指定的地址处的存储单元的功能。 存储单元优选地包括氧化物半导体晶体管。