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公开(公告)号：US20240268092A1
公开(公告)日：2024-08-08
申请号：US18638994
申请日：2024-04-18
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya ONUKI , Yuto YAKUBO , Seiya SAITO
CPC classification number: H10B12/00 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/24 , H01L29/78648 , H01L29/7869 , G11C5/06 , G11C8/08
Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.
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公开(公告)号：US20240257751A1
公开(公告)日：2024-08-01
申请号：US18560718
申请日：2022-05-17
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yuto YAKUBO , Kouhei TOYOTAKA , Seiko INOUE , Yoshiyuki KUROKAWA
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2310/08 , G09G2330/021 , G09G2360/14
Abstract: A semiconductor device including a display pixel circuit and an imaging pixel circuit is provided. The semiconductor device includes first and second circuits; the first circuit includes a light-emitting device; and the second circuit includes a light-receiving device, first to fifth transistors, and a first capacitor. The light-receiving device includes first and second terminals, and the light-emitting device includes third and fourth terminals. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor, and a gate of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the first capacitor. A second terminal of the first capacitor is electrically connected to a first terminal of the fourth transistor and a first terminal of the fifth transistor. A second terminal of the fifth transistor is electrically connected to the first terminal of the light-receiving device, the second terminal of the light-receiving device is electrically connected to the third terminal of the light-emitting device, and the fourth terminal of the light-emitting device is electrically connected to a wiring.
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公开(公告)号：US20210384355A1
公开(公告)日：2021-12-09
申请号：US17284553
申请日：2019-10-15
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Eri SATO , Tatsuya ONUKI , Yuto YAKUBO , Hitoshi KUNITAKI
IPC: H01L29/786 , H01L29/24
Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.
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公开(公告)号：US20150014419A1
公开(公告)日：2015-01-15
申请号：US14500343
申请日：2014-09-29
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO , Takaaki KOEN , Yuto YAKUBO , Makoto YANAGISAWA , Hisashi OHTANI , Eiji SUGIYAMA , Nozomi HORIKOSHI
IPC: G06K19/077
CPC classification number: G06K19/07735 , G06K19/07722 , G06K19/07794 , H01L23/295 , H01L23/3157 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.
Abstract translation: 一种能够进行无线通信的半导体装置，其在外力方面具有高的可靠性，特别是按压力，并且能够防止集成电路中的静电放电，而不会妨碍电波的接收。 半导体器件包括连接到集成电路的片上天线和将接收到的电波中包含的信号或功率发送到片上天线而不接触的增强天线。 在半导体器件中，集成电路和片上天线插入通过用树脂浸渍纤维体而形成的一对结构体之间。 其中一个结构体设置在片上天线和增强天线之间。 在每个结构体的至少一个表面上形成表面电阻值为大约106至1014Ω·cm 2 / cm 2的导电膜。
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公开(公告)号：US20240194252A1
公开(公告)日：2024-06-13
申请号：US18584118
申请日：2024-02-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiya SAITO , Yuto YAKUBO , Tatsuya ONUKI , Shuhei NAGATSUKA
IPC: G11C11/4097 , G11C11/4091 , H01L29/786 , H10B12/00
CPC classification number: G11C11/4097 , G11C11/4091 , H01L29/7869 , H10B12/30 , H10B12/50
Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.
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Patent Agency Ranking
公开(公告)号：US20230207567A1
公开(公告)日：2023-06-29
申请号：US17996516
申请日：2021-04-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Yuto YAKUBO , Shoki MIYATA , Akio SUZUKI , Takayuki IKEDA
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1207 , H01L29/7869 , H01L29/78681
Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a current-to-voltage conversion portion, a current switch portion, a voltage-to-current conversion portion, and a control portion. The current switch portion includes a first transistor. The voltage-to-current conversion portion includes a second transistor. The control portion includes a third transistor. The first transistor includes an oxide semiconductor in a channel formation region. The second transistor includes a nitride semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. The first transistor is provided over a first substrate. The second transistor and the third transistor are provided over a second substrate.
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公开(公告)号：US20220321006A1
公开(公告)日：2022-10-06
申请号：US17621338
申请日：2020-06-24
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Kousuke SASAKI , Yuto YAKUBO , Kei TAKAHASHI
IPC: H02M3/156 , H02H7/18 , H01L27/12 , H01L29/786
Abstract: A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.
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公开(公告)号：US20220085073A1
公开(公告)日：2022-03-17
申请号：US17422312
申请日：2019-11-19
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya ONUKI , Yuto YAKUBO , Yuki OKAMOTO , Seiya SAITO , Kiyoshi KATO , Shunpei YAMAZAKI
IPC: H01L27/12 , G11C11/4091 , G11C11/4096
Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.
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公开(公告)号：US20150294693A1
公开(公告)日：2015-10-15
申请号：US14681570
申请日：2015-04-08
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya ONUKI , Kiyoshi KATO , Yutaka SHIONOIRI , Tomoaki ATSUMI , Takanori MATSUZAKI , Hiroki INOUE , Shuhei NAGATSUKA , Yuto YAKUBO
CPC classification number: G11C5/025 , G11C11/4091 , G11C11/4097 , H01L27/1207 , H01L27/1225 , H01L29/24
Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.
Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。
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公开(公告)号：US20230291237A1
公开(公告)日：2023-09-14
申请号：US18040480
申请日：2021-08-02
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Yuto YAKUBO , Hiroshi KADOMA , Kaori OGITA
IPC: H02J50/10 , H01M10/633 , H01M10/6551 , H01M10/615
CPC classification number: H02J50/10 , H01M10/633 , H01M10/6551 , H01M10/615 , B60L58/27
Abstract: A control system for a secondary battery that effectively performs temperature control of the secondary battery before getting to a charging station, thereby enabling high speed charging, is provided. It relates to a vehicle including a first secondary battery, a second secondary battery, a first temperature control unit, a secondary battery monitoring unit, and an arithmetic unit. The secondary battery monitoring unit acquires remaining amount data of the first secondary battery. The arithmetic unit compares the remaining amount data and a set value. In the case where the remaining amount data is smaller than the set value, the secondary battery monitoring unit acquires the temperature of the first secondary battery. The arithmetic unit calculates an adjustment term required to adjust the temperature of the first secondary battery to a set temperature. The arithmetic unit calculates an arrival term required to get to a set charging station. The first temperature control unit starts adjusting the temperature of the first secondary battery to the set temperature, with electric power fed from the second secondary battery, in the case where the adjustment term is shorter than or equal to the arrival term.
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