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公开(公告)号：US11881280B2
公开(公告)日：2024-01-23
申请号：US17534136
申请日：2021-11-23
发明人： Shivam Kalla , Vikas Rana
IPC分类号： G05F3/02 , G05F1/10 , G11C5/14 , G11C11/56 , H02M1/00 , H03K5/24 , G05F3/26 , H02M3/07 , G11C16/30
CPC分类号： G11C5/145 , G05F3/262 , G11C5/147 , G11C11/5635 , G11C16/30 , H02M1/0003 , H02M3/07 , H03K5/24
摘要： An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.
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32.发明授权公开(公告)号：US11183924B2
公开(公告)日：2021-11-23
申请号：US17021013
申请日：2020-09-15
发明人： Vikas Rana
IPC分类号： H02M3/07 , H03K19/096 , G05F1/10
摘要： A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
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公开(公告)号：US10050524B1
公开(公告)日：2018-08-14
申请号：US15800896
申请日：2017-11-01
发明人： Vikas Rana
IPC分类号： H02M3/18 , H02M3/07 , H01L27/092 , H01L27/06 , H01L27/02
摘要： A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
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公开(公告)号：US09129685B2
公开(公告)日：2015-09-08
申请号：US14266468
申请日：2014-04-30
发明人： Vikas Rana
IPC分类号： G11C11/4193 , G11C11/4195 , G11C16/14 , G11C8/08 , G11C16/06 , G11C16/26
摘要： A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.
摘要翻译： 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。
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公开(公告)号：US12033715B2
公开(公告)日：2024-07-09
申请号：US18063041
申请日：2022-12-07
发明人： Vikas Rana , Arpit Vijayvergia
摘要： The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
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36.发明授权公开(公告)号：US11070128B2
公开(公告)日：2021-07-20
申请号：US16715209
申请日：2019-12-16
发明人： Vikas Rana , Shivam Kalla
摘要： A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.
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公开(公告)号：US10284201B1
公开(公告)日：2019-05-07
申请号：US15877970
申请日：2018-01-23
发明人： Vikas Rana
IPC分类号： H03L5/00 , H03K19/00 , H03K19/017 , H03K19/0185
摘要： A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.
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公开(公告)号：US10211727B1
公开(公告)日：2019-02-19
申请号：US16028814
申请日：2018-07-06
发明人： Vikas Rana
IPC分类号： H02M3/18 , H02M3/07 , H01L27/02 , H01L27/06 , H01L27/092
摘要： A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
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公开(公告)号：US10127990B1
公开(公告)日：2018-11-13
申请号：US15652564
申请日：2017-07-18
发明人： Vikas Rana
摘要： A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.
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公开(公告)号：US09755621B1
公开(公告)日：2017-09-05
申请号：US15162827
申请日：2016-05-24
发明人： Rohan Sinha , Vikas Rana
IPC分类号： H03L5/00 , H03K3/356 , H03K19/0185
CPC分类号： H03K3/356113 , H03K19/018521
摘要： A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.
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