公开(公告)号：US09305974B1

公开(公告)日：2016-04-05

申请号：US14688597

申请日：2015-04-16

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L29/66 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

公开(公告)号：US20160056249A1

公开(公告)日：2016-02-25

申请号：US14931078

申请日：2015-11-03

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  John Hongguang Zhang

IPC: H01L29/417 ,  H01L29/49 ,  H01L21/84

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

公开(公告)号：US09209305B1

公开(公告)日：2015-12-08

申请号：US14298000

申请日：2014-06-06

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

Abstract translation: 集成电路晶体管形成在衬底上和衬底中。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括在源极（或漏极）触点上方外延生长的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底优选为绝缘体上硅（SOI）型。

公开(公告)号：US10312261B2

公开(公告)日：2019-06-04

申请号：US15890910

申请日：2018-02-07

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L21/285 ,  H01L21/768 ,  H01L27/12 ,  H01L29/417 ,  H01L21/84 ,  H01L29/66

Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

公开(公告)号：US10121874B2

公开(公告)日：2018-11-06

申请号：US15485754

申请日：2017-04-12

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

Abstract: An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

公开(公告)号：US20180102395A1

公开(公告)日：2018-04-12

申请号：US15829397

申请日：2017-12-01

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars is stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

公开(公告)号：US09786551B2

公开(公告)日：2017-10-10

申请号：US14264803

申请日：2014-04-29

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John Hongguang Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L23/5228 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask.

公开(公告)号：US20170250198A1

公开(公告)日：2017-08-31

申请号：US15597337

申请日：2017-05-17

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/762 ,  H01L29/161 ,  H01L21/84 ,  H01L29/20 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L27/1203 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02675 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66628

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

公开(公告)号：US09640483B2

公开(公告)日：2017-05-02

申请号：US14724975

申请日：2015-05-29

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L29/80 ,  H01L23/535 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/535

Abstract: A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

公开(公告)号：US09543397B2

公开(公告)日：2017-01-10

申请号：US14931078

申请日：2015-11-03

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  John Hongguang Zhang

IPC: H01L21/00 ,  H01L29/417 ,  H01L29/786 ,  H01L27/12 ,  H01L21/84 ,  H01L29/49

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

Abstract translation: 集成电路晶体管形成在衬底上和衬底中。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括在源极（或漏极）触点上方外延生长的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底优选为绝缘体上硅（SOI）型。