中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

71 records (took 0.022 seconds)

    SYSTEM FOR THE MANAGEMENT OF OUT-OF-ORDER TRAFFIC IN AN INTERCONNECT NETWORK AND CORRESPONDING METHOD AND INTEGRATED CIRCUIT
    31.
    发明申请
    SYSTEM FOR THE MANAGEMENT OF OUT-OF-ORDER TRAFFIC IN AN INTERCONNECT NETWORK AND CORRESPONDING METHOD AND INTEGRATED CIRCUIT 审中-公开
    互连网络中的无序交通管理系统和相应的方法与集成电路

    公开(公告)号：US20150296018A1

    公开(公告)日：2015-10-15

    申请号：US14659159

    申请日：2015-03-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mirko Dondini ,  Daniele Mangano

    IPC: H04L29/08 ,  H04L12/721

    CPC classification number: H04L67/1097 ,  G06F13/1626 ,  G06F13/4022 ,  G06F2213/0038 ,  H04L45/72

    Abstract: A system to manage out-of-order traffic in an interconnect network has initiators that provide requests through the interconnect network to memory resource targets and provide responses back through the interconnect network. The system includes components upstream the interconnect network to perform response re-ordering, which include memory to store responses from the interconnect network and a memory map controller to store the responses on a set of logical circular buffers. Each logical circular buffer corresponds to an initiator. The memory map controller computes an offset address for each buffer and stores an offset address of a given request received on a request path. The controller computes an absolute write memory address where responses are written in the memory, the response corresponding to the given request based on the given request offset address. The memory map controller also performs an order-controlled parallel read of the logical circular buffers and routes the data read from the memory to the corresponding initiator.

    Abstract translation: 用于管理互连网络中的乱序流量的系统具有通过互连网络向存储器资源目标提供请求并且通过互连网络提供响应的启动器。 该系统包括互连网络上游的组件以执行响应重新排序，其包括用于存储来自互连网络的响应的存储器和存储映射控制器以将响应存储在一组逻辑循环缓冲器上。 每个逻辑循环缓冲区对应于启动器。 存储器映射控制器计算每个缓冲器的偏移地址，并存储在请求路径上接收的给定请求的偏移地址。 控制器计算绝对写存储器地址，其中响应被写入存储器中，该响应对应于给定的请求，基于给定的请求偏移地址。 存储器映射控制器还执行逻辑循环缓冲器的顺序控制的并行读取，并将从存储器读取的数据路由到相应的启动器。

    METHOD AND DEVICE FOR ABORTING TRANSACTIONS, RELATED SYSTEM AND COMPUTER PROGRAM PRODUCT
    32.
    发明申请
    METHOD AND DEVICE FOR ABORTING TRANSACTIONS, RELATED SYSTEM AND COMPUTER PROGRAM PRODUCT 有权
    用于交易的方法和设备，相关系统和计算机程序产品

    公开(公告)号：US20130297913A1

    公开(公告)日：2013-11-07

    申请号：US13888062

    申请日：2013-05-06

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Daniele Mangano

    IPC: G06F9/38

    CPC classification number: G06F9/3867 ,  G06F9/3861 ,  G06F9/466 ,  G06F9/485 ,  G06F11/0766 ,  G06F11/0793 ,  G06F13/1605

    Abstract: Current tasks being executed in a set of modules of a signal processing system managed via an interface block are aborted so as to permit the execution of new tasks by pipelining eliminating transactions of said current tasks and executing transactions of the new tasks. Upon arrival of a signal to abort the current tasks, data and/or memory accesses present in said interface block are discarded.

    Abstract translation: 在通过接口块管理的信号处理系统的一组模块中执行的当前任务被中止，以允许通过流水线去除所述当前任务的事务和执行新任务的交易来执行新任务。 当信号到达以中止当前任务时，丢弃存在于所述接口块中的数据和/或存储器访问。

    System and method for selecting an operating mode, such as a boot mode, of a micro-controller unit
    33.
    发明授权
    System and method for selecting an operating mode, such as a boot mode, of a micro-controller unit 有权

    公开(公告)号：US11705904B2

    公开(公告)日：2023-07-18

    申请号：US17671844

    申请日：2022-02-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Mangano ,  Alessandro Inglese

    IPC: H03K19/0175 ,  G06F13/12

    CPC classification number: H03K19/017581 ,  G06F13/124

    Abstract: A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.

    Power management method, corresponding system and apparatus
    35.
    发明授权
    Power management method, corresponding system and apparatus 有权

    公开(公告)号：US11025289B2

    公开(公告)日：2021-06-01

    申请号：US16800793

    申请日：2020-02-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Mangano ,  Pasquale Butta′

    IPC: H04B1/40 ,  H02M1/00

    Abstract: A method for power management in an electronic circuit that comprises a processing system and an RF embedded circuit includes: generating a first regulated voltage with a power regulation module of the RF embedded circuit; generating a second regulated voltage from the first regulated voltage with a first linear regulator of the processing system; and controlling the power regulation module of the RF embedded circuit to operate according to a plurality of operation modes. The operation modes include: a first sleep mode in which a switched-mode power supply of the RF embedded circuit is off and a second linear regulator of the RF embedded circuit is off; a second sleep mode in which a switched-mode power supply is off and the second linear regulator is on; and a third sleep mode in which the switched-mode power supply is on and the second linear regulator is off.

    POWER MANAGEMENT METHOD, CORRESPONDING SYSTEM AND APPARATUS
    36.
    发明申请
    POWER MANAGEMENT METHOD, CORRESPONDING SYSTEM AND APPARATUS 审中-公开

    公开(公告)号：US20200280332A1

    公开(公告)日：2020-09-03

    申请号：US16800793

    申请日：2020-02-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Mangano ,  Pasquale Butta'

    IPC: H04B1/40 ,  H02M1/00

    Abstract: A method for power management in an electronic circuit that comprises a processing system and an RF embedded circuit includes: generating a first regulated voltage with a power regulation module of the RF embedded circuit; generating a second regulated voltage from the first regulated voltage with a first linear regulator of the processing system; and controlling the power regulation module of the RF embedded circuit to operate according to a plurality of operation modes. The operation modes include: a first sleep mode in which a switched-mode power supply of the RF embedded circuit is off and a second linear regulator of the RF embedded circuit is off; a second sleep mode in which a switched-mode power supply is off and the second linear regulator is on; and a third sleep mode in which the switched-mode power supply is on and the second linear regulator is off.

    SYSTEM AND METHOD FOR SELECTING A CLOCK
    37.
    发明申请
    SYSTEM AND METHOD FOR SELECTING A CLOCK 审中-公开

    公开(公告)号：US20200278393A1

    公开(公告)日：2020-09-03

    申请号：US16791020

    申请日：2020-02-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mirko Dondini ,  Daniele Mangano ,  Salvatore Pisasale

    IPC: G01R31/3185 ,  G01R31/319 ,  G01R29/027 ,  G06F1/08 ,  G06F1/12 ,  G06F13/24

    Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.

    Method and system for performing division/multiplication operations in digital processors, corresponding device and computer program product
    38.
    发明授权
    Method and system for performing division/multiplication operations in digital processors, corresponding device and computer program product 有权

    公开(公告)号：US10108396B2

    公开(公告)日：2018-10-23

    申请号：US14313273

    申请日：2014-06-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Mangano

    IPC: G06F5/01 ,  G06F7/52 ,  G06F7/523 ,  G06F7/535

    Abstract: A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.

Patent Agency Ranking