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公开(公告)号：US09959226B2
公开(公告)日：2018-05-01
申请号：US14841522
申请日：2015-08-31
CPC分类号： G06F13/28 , G06F3/0619 , G06F3/0655 , G06F3/067 , G06F13/4059 , G06F2213/0038
摘要： A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
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公开(公告)号：US20130259146A1
公开(公告)日：2013-10-03
申请号：US13854419
申请日：2013-04-01
CPC分类号： H03M13/6522 , G06F13/4286 , H03M13/51
摘要： A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.
摘要翻译： 一种完成检测器电路，用于检测在根据延迟不敏感编码（例如，双轨，m-of-n，Berger编码）组织的信号线在通信信道上完成异步数据的传输，包括：用于 检测上述信号线上的数据，其配置用于：i）产生指示信号线上的异步数据是稳定的事实的第一信号; ii）产生指示信号线被断言的事实的第二信号; 以及提供有第一信号和第二信号的异步有限状态机，用于产生检测异步数据传输完成的信号，检测信号具有：第一值，当第一信号被断言时; 以及第二值，当所述第二信号被断言时; 并且当所述第一信号和所述第二信号的一个或另一个被断言时，它们处于保持状态。
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公开(公告)号：US20200278393A1
公开(公告)日：2020-09-03
申请号：US16791020
申请日：2020-02-14
IPC分类号： G01R31/3185 , G01R31/319 , G01R29/027 , G06F1/08 , G06F1/12 , G06F13/24
摘要： In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.
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4.发明申请公开(公告)号：US20150370734A1
公开(公告)日：2015-12-24
申请号：US14841522
申请日：2015-08-31
CPC分类号： G06F13/28 , G06F3/0619 , G06F3/0655 , G06F3/067 , G06F13/4059 , G06F2213/0038
摘要： A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
摘要翻译： 通信接口将传输电路与互连网络耦合。 发送电路请求发送预定量的数据。 通信接口从发送电路接收数据段，将数据段存储在存储器中，并且验证存储器是否包含预定量的数据。 在存储器包含预定量的数据的情况下，通信接口开始存储在存储器中的数据的发送。 或者，在存储器包含小于预定数据量的数据量的情况下，通信接口确定从上述发送电路接收到从发送请求或第一基准开始经过的时间的参数， 并验证所经过的时间是否超过时间阈值。 在经过时间超过时间阈值的情况下，通信接口开始存储在存储器中的数据的发送。
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公开(公告)号：US20150207581A1
公开(公告)日：2015-07-23
申请号：US14604439
申请日：2015-01-23
CPC分类号： H04L43/0858 , G06F1/04 , G06F13/4291 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/10
摘要： A communication system for interfacing a transmitting circuit with a receiving circuit includes a transmission interface for receiving data from the transmitting circuit and transmitting the data received over at least one data line in response to a transmission clock signal. The communication system also includes a reception interface configured for receiving the data in response to a reception clock signal and transmitting the data received to the receiving circuit. In particular, the system is configured for generating a plurality of clock signals that have the same frequency but are phase-shifted with respect to one another. In addition, during a calibration phase, the system is configured for selecting one of the clock signals for the transmission clock signal or reception clock signal via selecting at least one of the clock signals for transmission of test signals via the transmission interface and verifying whether the test signals received via the reception interface are correct. The system is further configured to use, during normal operation, the clock signal selected during the calibration phase for transmission of data.
摘要翻译： 用于将发射电路与接收电路接口的通信系统包括用于从发射电路接收数据的传输接口，并响应于传输时钟信号发射通过至少一条数据线接收的数据。 通信系统还包括：接收接口，被配置为响应于接收时钟信号接收数据，并将接收到的数据发送到接收电路。 特别地，该系统被配置为产生具有相同频率但是相对于彼此相移的多个时钟信号。 此外，在校准阶段期间，系统被配置为通过经由传输接口选择用于传输测试信号的时钟信号中的至少一个来选择传输时钟信号或接收时钟信号中的一个时钟信号，并且验证 通过接收接口接收到的测试信号是正确的。 该系统还被配置为在正常操作期间使用在校准阶段期间选择的用于传输数据的时钟信号。
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公开(公告)号：US11644504B2
公开(公告)日：2023-05-09
申请号：US16791020
申请日：2020-02-14
IPC分类号： G01R31/3185 , G01R29/027 , G01R31/319 , G06F1/08 , G06F1/12 , G06F13/24
CPC分类号： G01R31/318552 , G01R29/0273 , G01R31/31922 , G01R31/318594 , G06F1/08 , G06F1/12 , G06F13/24
摘要： In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.
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公开(公告)号：US10579561B2
公开(公告)日：2020-03-03
申请号：US15940650
申请日：2018-03-29
摘要： A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
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公开(公告)号：US09692672B2
公开(公告)日：2017-06-27
申请号：US14604439
申请日：2015-01-23
CPC分类号： H04L43/0858 , G06F1/04 , G06F13/4291 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/10
摘要： A communication system for interfacing a transmitting circuit with a receiving circuit includes a transmission interface for receiving data from the transmitting circuit and transmitting the data received over at least one data line in response to a transmission clock signal. The communication system also includes a reception interface configured for receiving the data in response to a reception clock signal and transmitting the data received to the receiving circuit. In particular, the system is configured for generating a plurality of clock signals that have the same frequency but are phase-shifted with respect to one another. In addition, during a calibration phase, the system is configured for selecting one of the clock signals for the transmission clock signal or reception clock signal via selecting at least one of the clock signals for transmission of test signals via the transmission interface and verifying whether the test signals received via the reception interface are correct. The system is further configured to use, during normal operation, the clock signal selected during the calibration phase for transmission of data.
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公开(公告)号：US09191033B2
公开(公告)日：2015-11-17
申请号：US13854419
申请日：2013-04-01
CPC分类号： H03M13/6522 , G06F13/4286 , H03M13/51
摘要： A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.
摘要翻译： 一种完成检测器电路，用于检测在根据延迟不敏感编码（例如，双轨，m-of-n，Berger编码）组织的信号线在通信信道上完成异步数据的传输，包括：用于 检测上述信号线上的数据，其配置用于：i）产生指示信号线上的异步数据是稳定的事实的第一信号; ii）产生指示信号线被断言的事实的第二信号; 以及提供有第一信号和第二信号的异步有限状态机，用于产生检测异步数据传输完成的信号，检测信号具有：第一值，当第一信号被断言时; 以及第二值，当所述第二信号被断言时; 并且当所述第一信号和所述第二信号的一个或另一个被断言时，它们处于保持状态。
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公开(公告)号：US08990436B2
公开(公告)日：2015-03-24
申请号：US13904379
申请日：2013-05-29
CPC分类号： G06F9/466 , G06F13/1626 , G06F2213/0038
摘要： In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.
摘要翻译： 在一个实施例中，通过分配经过一致性检查的事务标识符来管理诸如片上系统（SoC）的系统的至少一个模块到诸如存储器的多个目标模块之一的访问事务。 如果已经为相同的给定目标模块发出了支票的输入标识符，则向相关标识符/给定目标模块对发送相同的输入标识符作为一致的输出标识符。 相反，如果相对于所述检查的所述输入标识符尚未被发布或者已经针对与所考虑的目标模块不同的目标模块已经被发布到相关标识符/给定目标模块对，则与输入标识符不同的新标识符 ，被分配为一致的输出标识符。
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