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公开(公告)号：US20180330787A1
公开(公告)日：2018-11-15
申请号：US16044280
申请日：2018-07-24
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
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公开(公告)号：US10050524B1
公开(公告)日：2018-08-14
申请号：US15800896
申请日：2017-11-01
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/18 , H02M3/07 , H01L27/092 , H01L27/06 , H01L27/02
Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
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公开(公告)号：US20170178727A1
公开(公告)日：2017-06-22
申请号：US15433795
申请日：2017-02-15
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
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公开(公告)号：US09129685B2
公开(公告)日：2015-09-08
申请号：US14266468
申请日：2014-04-30
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: G11C11/4193 , G11C11/4195 , G11C16/14 , G11C8/08 , G11C16/06 , G11C16/26
Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.
Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。
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35.发明授权公开(公告)号：US11935607B2
公开(公告)日：2024-03-19
申请号：US17837377
申请日：2022-06-10
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Vivek Tyagi
CPC classification number: G11C29/12005 , G11C29/18 , G11C29/4401 , G11C29/52 , G11C2029/1202 , G11C2029/1204 , G11C2029/1802
Abstract: An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.
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Patent Agency Ranking
公开(公告)号：US11908528B2
公开(公告)日：2024-02-20
申请号：US17527031
申请日：2021-11-15
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Vikas Rana , Arpit Vijayvergia
Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.
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37.发明授权公开(公告)号：US11563373B2
公开(公告)日：2023-01-24
申请号：US17494451
申请日：2021-10-05
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Neha Dalal
Abstract: A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes: a first switched circuit coupled to a first output of the first charge pump stage circuit and configured, when actuated, to discharge the first output; and a second switched circuit coupled to a second output of the second charge pump stage circuit and configured, when actuated, to discharge the second output. A discharge control circuit actuates the first switched discharge circuit to discharge the first output and then, after the first output is fully discharged, actuates the second switched discharge circuit to discharge the second output.
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公开(公告)号：US11551731B2
公开(公告)日：2023-01-10
申请号：US17321344
申请日：2021-05-14
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Arpit Vijayvergia
Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
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39.发明授权公开(公告)号：US11258358B2
公开(公告)日：2022-02-22
申请号：US16742248
申请日：2020-01-14
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Shivam Kalla
IPC: H02M3/07
Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.
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40.发明授权公开(公告)号：US10811960B2
公开(公告)日：2020-10-20
申请号：US16563069
申请日：2019-09-06
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07 , G05F1/10 , H03K19/096
Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
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