公开(公告)号：US12033715B2

公开(公告)日：2024-07-09

申请号：US18063041

申请日：2022-12-07

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Arpit Vijayvergia

IPC: G11C7/00 ,  G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  H03K19/20

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

公开(公告)号：US11070128B2

公开(公告)日：2021-07-20

申请号：US16715209

申请日：2019-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Shivam Kalla

IPC: H02M3/07 ,  G11C16/30 ,  G11C5/14

Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.

公开(公告)号：US10284201B1

公开(公告)日：2019-05-07

申请号：US15877970

申请日：2018-01-23

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas Rana

IPC: H03L5/00 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185

Abstract: A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.

公开(公告)号：US10211727B1

公开(公告)日：2019-02-19

申请号：US16028814

申请日：2018-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/18 ,  H02M3/07 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092

Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

公开(公告)号：US10127990B1

公开(公告)日：2018-11-13

申请号：US15652564

申请日：2017-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/14 ,  G11C16/08

Abstract: A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.

公开(公告)号：US09755621B1

公开(公告)日：2017-09-05

申请号：US15162827

申请日：2016-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Rohan Sinha ,  Vikas Rana

IPC: H03L5/00 ,  H03K3/356 ,  H03K19/0185

CPC classification number: H03K3/356113 ,  H03K19/018521

Abstract: A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.

公开(公告)号：US09325323B2

公开(公告)日：2016-04-26

申请号：US14474091

申请日：2014-08-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas Rana ,  Ganesh Raj R

IPC: H03K3/03 ,  H03L1/00 ,  H03L7/14 ,  H03L7/18 ,  H03L7/093 ,  H03L7/089 ,  H03L7/081 ,  H03L7/099

CPC classification number: H03L1/00 ,  H03K3/011 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L1/022 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/0997 ,  H03L7/148 ,  H03L7/18

Abstract: A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.

Abstract translation: 时钟信号生成电路，被配置为生成具有在诸如电源电压，温度和处理时间的变化的操作条件的数量的变化中保持的频率的时钟信号。 在一个实施例中，PVT补偿的CMOS环形振荡器的所产生的时钟信号的频率扩展被配置为补偿电源电压的变化，以及通过处理和温度补偿电路对工艺和温度的变化。 PVT补偿的CMOS环形振荡器包括一个稳压电源，用于产生一个电源电压，该电源电压抵抗由于整个电源电压的变化引起的变化。

公开(公告)号：US11522446B2

公开(公告)日：2022-12-06

申请号：US17494244

申请日：2021-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07 ,  G05F1/59 ,  H02M1/00

Abstract: The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

公开(公告)号：US11356018B2

公开(公告)日：2022-06-07

申请号：US17313533

申请日：2021-05-06

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07

Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.

公开(公告)号：US10333397B2

公开(公告)日：2019-06-25

申请号：US15652748

申请日：2017-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Abhishek Mittal

IPC: H02M3/07

Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.