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公开(公告)号：US20140183535A1
公开(公告)日：2014-07-03
申请号：US13875722
申请日：2013-05-02
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Shin Il CHOI , Sang Gab KIM , Su Bin BAE , Yu-Gwang JEONG
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1248 , H01L27/322 , H01L27/3248
Abstract: A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate, a gate line disposed on the substrate and including a gate electrode, a gate insulating layer disposed on the gate line, a semiconductor disposed on the gate insulating layer, a data line disposed on the semiconductor and including a source electrode, a drain electrode disposed on the semiconductor and opposite to the source electrode, a color filter disposed on the gate insulating layer, the data line and the drain electrode, an overcoat disposed on the color filter and including an inorganic material, a contact hole defined in the color filter and the overcoat, where the contact hole exposes the drain electrode, and a pixel electrode disposed on the overcoat and connected through the contact hole to the drain electrode, in which a plane shape of the contact hole in the overcoat and a plane shape of the contact hole in the color filter are substantially the same as each other.
Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：衬底，设置在衬底上并包括栅电极的栅极线，设置在栅极线上的栅极绝缘层，设置在栅极绝缘层上的半导体 ，设置在半导体上的数据线，包括源电极，设置在半导体上并与源电极相对的漏电极，布置在栅绝缘层上的滤色器，数据线和漏电极， 所述滤色器包括无机材料，所述滤色器中限定的接触孔和所述外涂层，其中所述接触孔暴露于所述漏电极，以及设置在所述外涂层上并通过所述接触孔连接到所述漏电极的像素电极， 外涂层中的接触孔的平面形状和滤色器中的接触孔的平面形状基本上与每个 r。
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公开(公告)号：US20140159059A1
公开(公告)日：2014-06-12
申请号：US13869697
申请日：2013-04-24
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Yu-Gwang JEONG , Ji-Young PARK , Shin-Il CHOI , Sang-Gab KIM
IPC: H01L33/02
CPC classification number: H01L27/124 , G02F1/133707 , H01L27/1248 , H01L27/1288
Abstract: A method of manufacturing a display substrate includes forming a gate insulation layer on the base substrate on which a gate metal pattern, forming a data metal pattern on the gate insulation layer, sequentially forming a insulation layer and an organic layer on the base substrate on which the data metal pattern is formed, partially exposing the organic layer, developing the organic layer to partially remove the organic layer on the data metal pattern and to expose at least a portion of the protecting layer on the gate metal pattern, forming a common electrode on the organic layer, forming a pixel electrode on the on the organic layer, and forming an insulation layer between the pixel electrode and the common electrode. An etching degree of a data metal may be controlled by controlling a thickness of a remained organic layer to reduce a damage of the data metal.
Abstract translation: 一种制造显示基板的方法包括在基底基板上形成栅极绝缘层，栅基金属图案在栅绝缘层上形成数据金属图案，在基底基板上依次形成绝缘层和有机层， 形成数据金属图案，部分地暴露有机层，显影有机层以部分地去除数据金属图案上的有机层，并暴露栅极金属图案上的保护层的至少一部分，形成公共电极 有机层，在有机层上形成像素电极，在像素电极和公共电极之间形成绝缘层。 可以通过控制剩余的有机层的厚度来减少数据金属的损伤来控制数据金属的蚀刻程度。
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公开(公告)号：US20140147947A1
公开(公告)日：2014-05-29
申请号：US14168971
申请日：2014-01-30
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Yu-Gwang JEONG , Young-Wook LEE , Sang-Gab KIM , Woo-Geun LEE , Min-Seok OH , Jang-Soo KIM , Kap-Soo YOON , Shin-Il CHOI , Hong-Kee CHIN , Seung-Ha CHOI , Seung-Hwan SHIM , Sung-Hoon YANG , Ki-Hun JEONG
IPC: H01L27/12
CPC classification number: H01L27/127 , H01L27/1214 , H01L27/1259 , H01L27/1288 , H01L29/66765
Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.
Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。
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34.发明公开公开(公告)号：US20230215954A1
公开(公告)日：2023-07-06
申请号：US18176454
申请日：2023-02-28
Applicant: SAMSUNG DISPLAY CO., LTD
Inventor： YONG SU LEE , Yoon Ho KHANG , Dong Jo KIM , Hyun Jae NA , Sang Ho PARK , Se Hwan YU , Chong Sup CHANG , Dae Ho KIM , Jae Neung Kim , Myoung Geun CHA , Sang Gab KIM , Yu-Gwang JEONG
IPC: H01L29/786 , H01L27/12 , H01L29/66 , H01L29/417
CPC classification number: H01L29/78633 , H01L29/78618 , H01L27/1288 , H01L27/124 , H01L29/7869 , H01L27/1225 , H01L29/78696 , H01L29/66969 , H01L29/41733 , H10K59/1213
Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
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公开(公告)号：US20230200113A1
公开(公告)日：2023-06-22
申请号：US17881693
申请日：2022-08-05
Applicant: Samsung Display Co., LTD.
Inventor： Yu-Gwang JEONG , Jin-Su BYUN , Sung Won CHO , Su Bin BAE , DAWOON JUNG
CPC classification number: H01L51/5253 , H01L27/323 , H01L51/56 , H01L27/3276 , H01L2227/323
Abstract: A display device includes a display area, anon-display area, and a pad part in the non-display area and exposed to outside the display device. The pad part includes a conductive part, and an insulating part defining an opening exposing the conductive part to outside the pad part. The insulating part includes in order from the conductive part a first insulating layer defining a first opening, and a second insulating layer facing the first insulating layer and defining a second opening which is wider than the first opening.
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Patent Agency Ranking
公开(公告)号：US20230180537A1
公开(公告)日：2023-06-08
申请号：US17860206
申请日：2022-07-08
Applicant: Samsung Display Co., Ltd.
Inventor： DAWOON JUNG , Dae Won CHOI , Su Bin BAE , Yu-Gwang JEONG
CPC classification number: H01L27/3248 , H01L51/5072 , H01L51/5056 , H01L27/3246 , H01L2251/305
Abstract: A light emitting display device includes a substrate, a transistor, a first insulating layer, a second insulating layer, a pixel electrode, a conductive member, a third insulating layer, and a light emitting material layer. The transistor overlaps the substrate. The first insulating layer overlaps the transistor. The second insulating layer overlaps the first insulating layer. The pixel electrode directly contacts the second insulating layer and is electrically connected to the transistor. The conductive member directly contacts at least one of the first insulating layer and the second insulating layer. The third insulating layer overlaps the second insulating layer, includes a hole, and includes an opening. The hole exposes the pixel electrode. The opening exposes the conductive member. The light emitting material layer overlaps the pixel electrode inside the hole, overlaps the third insulating layer, and has a discontinuity inside the opening.
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37.发明申请公开(公告)号：US20220415932A1
公开(公告)日：2022-12-29
申请号：US17822751
申请日：2022-08-26
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Sungwon CHO , Yu-Gwang JEONG , Daewon CHOI , Seon-Il KIM , Subin BAE , Yun Jong YEO
IPC: H01L27/12 , H01L29/786
Abstract: A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.
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38.发明申请公开(公告)号：US20210074784A1
公开(公告)日：2021-03-11
申请号：US16953188
申请日：2020-11-19
Applicant: Samsung Display Co., Ltd.
Inventor： Sang Gab KIM , Hyunmin CHO , Taesung KIM , Subin BAE , Yu-Gwang JEONG , Jinseock KIM
Abstract: A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.
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39.发明申请公开(公告)号：US20200168684A1
公开(公告)日：2020-05-28
申请号：US16681697
申请日：2019-11-12
Applicant: Samsung Display Co., Ltd.
Inventor： Sang Gab KIM , Hyunmin CHO , Taesung KIM , Subin BAE , Yu-Gwang JEONG , Jinseock KIM
Abstract: A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.
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公开(公告)号：US20190123065A1
公开(公告)日：2019-04-25
申请号：US16215520
申请日：2018-12-10
Applicant: Samsung Display Co., Ltd.
Inventor： Yu-Gwang JEONG , Hyun Min CHO , Su Bin BAE , Shin II CHOI , Sang Gab KIM
IPC: H01L27/12 , H01L21/311 , H01L29/417
CPC classification number: H01L27/124 , G02F1/1368 , G02F2201/123 , H01L21/31116 , H01L21/31144 , H01L27/1218 , H01L27/1288 , H01L27/3246 , H01L27/3248 , H01L27/3262 , H01L27/3276 , H01L29/41733 , H01L29/78633
Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.
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