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    Ferroelectric-based memory cell usable in on-logic chip memory
    31.
    发明授权
    Ferroelectric-based memory cell usable in on-logic chip memory 有权

    公开(公告)号：US10679688B2

    公开(公告)日：2020-06-09

    申请号：US16142954

    申请日：2018-09-26

    Applicant: Samsung Electronics Co., LTD.

    Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl

    IPC: G11C11/22 ,  H01L27/11585 ,  H01L27/11502

    Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.

    FERROELECTRIC-BASED MEMORY CELL USABLE IN ON-LOGIC CHIP MEMORY
    32.
    发明申请
    FERROELECTRIC-BASED MEMORY CELL USABLE IN ON-LOGIC CHIP MEMORY 审中-公开

    公开(公告)号：US20190318775A1

    公开(公告)日：2019-10-17

    申请号：US16142954

    申请日：2018-09-26

    Applicant: Samsung Electronics Co., LTD.

    Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl

    IPC: G11C11/22

    Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.

    METHOD AND SYSTEM FOR PERFORMING ANALOG COMPLEX VECTOR-MATRIX MULTIPLICATION
    34.
    发明申请
    METHOD AND SYSTEM FOR PERFORMING ANALOG COMPLEX VECTOR-MATRIX MULTIPLICATION 审中-公开

    公开(公告)号：US20190080230A1

    公开(公告)日：2019-03-14

    申请号：US15849106

    申请日：2017-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

    IPC: G06N3/063 ,  G06F7/544

    Abstract: A hardware device and method for performing a multiply-accumulate operation are described. The device includes inputs lines, weight cells and output lines. The input lines receive input signals, each of which is has a magnitude and a phase and can represent a complex value. The weight cells couple the input lines with the output lines. Each of the weight cells has an electrical admittance corresponding to a weight. The electrical admittance is programmable and capable of being complex valued. The input lines, the weight cells and the output lines form a crossbar array. Each of the output lines provides an output signal. The output signal for an output line is a sum of an input signal for each of the input lines connected to the output line multiplied by the electrical admittance of each of the weight cells connecting the input lines to the output line.

    SELECTORLESS, 3D STACKABLE CROSSPOINT MEMORY
    35.
    发明申请
    SELECTORLESS, 3D STACKABLE CROSSPOINT MEMORY 审中-公开

    公开(公告)号：US20190079701A1

    公开(公告)日：2019-03-14

    申请号：US15845985

    申请日：2017-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Vladimir Nikitin ,  Dmytro Apalkov

    IPC: G06F3/06 ,  H01L21/3105 ,  H01L21/822 ,  H01L27/11578

    Abstract: A memory device and method for providing the memory device are described. The memory device includes word lines, a first plurality of bit lines, a second plurality of bit lines and selectorless memory cells. Each selectorless memory cell is coupled with a word line, a first bit line of the first plurality of bit lines and a second bit line of the second plurality of bit lines. The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque. The word line is coupled between the first and second magnetic junctions. The first and second bit lines are coupled with the first and second magnetic junctions, respectively. The selectorless memory cell is selected for a write operation based on voltages in the word line, the first bit line and the second bit line.

    VARIABLE PRECISION NEUROMORPHIC ARCHITECTURE
    36.
    发明申请
    VARIABLE PRECISION NEUROMORPHIC ARCHITECTURE 审中-公开

    公开(公告)号：US20190026627A1

    公开(公告)日：2019-01-24

    申请号：US15891220

    申请日：2018-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

    IPC: G06N3/063 ,  G06N3/04

    Abstract: A neuromorphic architecture for providing variable precision in a neural network, through programming. Logical pre-synaptic neurons are formed as configurable sets of physical pre-synaptic artificial neurons, logical post-synaptic neurons are formed as configurable sets of physical post-synaptic artificial neurons, and the logical pre-synaptic neurons are connected to the logical post-synaptic neurons by logical synapses each including a set of physical artificial synapses. The precision of the weights of the logical synapses may be varied by varying the number of physical pre-synaptic artificial neurons in each of the logical pre-synaptic neurons, and/or by varying the number of physical post-synaptic artificial neurons in each of the logical post-synaptic neurons.

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