公开(公告)号：US10312243B2

公开(公告)日：2019-06-04

申请号：US15920628

申请日：2018-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

IPC: H01L29/43 ,  H01L29/49 ,  H01L27/108 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/51

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

公开(公告)号：US20190115351A1

公开(公告)日：2019-04-18

申请号：US15966554

申请日：2018-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： NAMHO JEON ,  Jin-Seong LEE ,  Hyun-jung LEE ,  Dongsoo Woo ,  Donggyu HEO ,  Jaeho Hong

IPC: H01L27/105 ,  H01L21/8239 ,  H01L21/8238 ,  H01L29/06

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

公开(公告)号：US09905659B2

公开(公告)日：2018-02-27

申请号：US15011820

申请日：2016-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junsoo Kim ,  Moonyoung Jeong ,  Satoru Yamada ,  Dongsoo Woo ,  Jiyoung Kim

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/108 ,  H01L27/088

CPC classification number: H01L29/402 ,  H01L27/088 ,  H01L27/10876 ,  H01L29/42392

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US09449677B2

公开(公告)日：2016-09-20

申请号：US14537387

申请日：2014-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Yongchul Oh ,  Dongsoo Woo ,  Hyun-Woo Chung ,  Gyoyoung Jin ,  Sungkwan Choi ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: G11C11/40 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/404 ,  G11C11/408 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Abstract translation: 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。