公开(公告)号：US11908867B2

公开(公告)日：2024-02-20

申请号：US18157591

申请日：2023-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoung-Sun Lee ,  Keun Hwi Cho

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/7848

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

公开(公告)号：US11837638B2

公开(公告)日：2023-12-05

申请号：US17335413

申请日：2021-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon Lee ,  Chang Woo Sohn ,  Keun Hwi Cho ,  Sang Won Baek

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/6684 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.

公开(公告)号：US20230139574A1

公开(公告)日：2023-05-04

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGGUN YOU ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US11588054B2

公开(公告)日：2023-02-21

申请号：US17240616

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20230049858A1

公开(公告)日：2023-02-16

申请号：US17720741

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Keun Hwi Cho ,  Daewon Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

公开(公告)号：US11296204B2

公开(公告)日：2022-04-05

申请号：US16418705

申请日：2019-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok Ha ,  Gukil An ,  Keun Hwi Cho ,  Sungmin Kim

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

公开(公告)号：US20210020636A1

公开(公告)日：2021-01-21

申请号：US16789588

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoung-Sun LEE ,  Keun Hwi Cho

IPC: H01L27/092 ,  H01L27/02

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

公开(公告)号：US12237391B2

公开(公告)日：2025-02-25

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US12183800B2

公开(公告)日：2024-12-31

申请号：US18449734

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US12142650B2

公开(公告)日：2024-11-12

申请号：US18495292

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon Lee ,  Chang Woo Sohn ,  Keun Hwi Cho ,  Sang Won Baek

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.