公开(公告)号：US11869775B2

公开(公告)日：2024-01-09

申请号：US18169161

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/485 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/73 ,  H01L21/60 ,  H01L2224/023 ,  H01L2224/0508 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US20230197469A1

公开(公告)日：2023-06-22

申请号：US18169161

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/485 ,  H01L21/60

CPC classification number: H01L21/563 ,  H01L24/73 ,  H01L24/13 ,  H01L24/05 ,  H01L23/49816 ,  H01L23/485 ,  H01L2224/05548 ,  H01L2224/05022 ,  H01L2924/15311 ,  H01L21/60 ,  H01L2224/13024 ,  H01L2224/0508 ,  H01L2224/73204 ,  H01L2224/023

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US20230187345A1

公开(公告)日：2023-06-15

申请号：US18105945

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L23/3128 ,  H01L23/5283 ,  H01L21/565 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76819 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0231 ,  H01L2224/02373

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

公开(公告)号：US11637081B2

公开(公告)日：2023-04-25

申请号：US17474614

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

公开(公告)号：US20230085930A1

公开(公告)日：2023-03-23

申请号：US18060853

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US11600564B2

公开(公告)日：2023-03-07

申请号：US17189964

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

公开(公告)号：US11348876B2

公开(公告)日：2022-05-31

申请号：US17130505

申请日：2020-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Seung-Kwan Ryu ,  Seokhyun Lee

IPC: H01L21/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L23/498

Abstract: A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

公开(公告)号：US11094636B2

公开(公告)日：2021-08-17

申请号：US16671625

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Inwon O ,  Jongyoun Kim ,  Seokhyun Lee ,  Yeonho Jang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L23/66 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.

公开(公告)号：US10756015B2

公开(公告)日：2020-08-25

申请号：US16703233

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyung Suk Oh

IPC: H01L29/80 ,  H01L31/0288 ,  H01L31/112 ,  H01L23/522 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L21/768

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided.

公开(公告)号：US10546829B2

公开(公告)日：2020-01-28

申请号：US15867075

申请日：2018-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Ji Min ,  Seokhyun Lee ,  Jongyoun Kim ,  Kyoung Lim Suk ,  SeokWon Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/10

Abstract: A method of fabricating a semiconductor package including forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.