-
公开(公告)号：US12022658B2
公开(公告)日：2024-06-25
申请号：US18356064
申请日：2023-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
-
公开(公告)号：US11974438B2
公开(公告)日：2024-04-30
申请号：US17903315
申请日：2022-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Haemin Lee , Jongwon Kim , Shinhwan Kang , Kohji Kanamori , Jeehoon Han
Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.
-
公开(公告)号：US20240121957A1
公开(公告)日：2024-04-11
申请号：US18240017
申请日：2023-08-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myunghoon Han , Sehee Jang , Hyunho Kim , Jeehoon Han
CPC classification number: H10B43/27 , H01L23/562 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35
Abstract: A semiconductor device includes a gate electrode structure, a memory channel structure, a first division pattern, and first support patterns. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The memory channel structure extends through the gate electrode structure on the substrate. The first division pattern is formed on a sidewall of the gate electrode structure in a third direction parallel to the upper surface of the substrate and crossing the second direction, and extends in the second direction. The first support patterns are spaced apart from each other in the second direction on the first division pattern, and each of the first support patterns includes a conductive material.
-
公开(公告)号：US20240105604A1
公开(公告)日：2024-03-28
申请号：US18526208
申请日：2023-12-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Hun Lee , Seokjung Yun , Chang-Sup Lee , Seong Soon Cho , Jeehoon Han
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H10B41/20 , H10B41/27 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/35 , H10B43/50
CPC classification number: H01L23/5283 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H10B41/20 , H10B41/27 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/35 , H10B43/50
Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.
-
公开(公告)号：US20230371260A1
公开(公告)日：2023-11-16
申请号：US18356064
申请日：2023-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
-
Patent Agency Ranking
公开(公告)号：US11778834B2
公开(公告)日：2023-10-03
申请号：US17983024
申请日：2022-11-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
-
37.发明授权公开(公告)号：US11374017B2
公开(公告)日：2022-06-28
申请号：US16842055
申请日：2020-04-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji Kanamori , Seogoo Kang , Jongseon Ahn , Jeehoon Han
IPC: H01L27/1157 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/11565 , H01L27/11573 , H01L29/49 , H01L21/28 , H01L27/11519 , H01L27/11582
Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.
-
38.发明申请公开(公告)号：US20210091093A1
公开(公告)日：2021-03-25
申请号：US16842055
申请日：2020-04-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji Kanamori , Seogoo Kang , Jongseon Ahn , Jeehoon Han
IPC: H01L27/1157 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573 , H01L29/49 , H01L21/28 , H01L27/11519 , H01L27/11565
Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.
-
公开(公告)号：US20210074720A1
公开(公告)日：2021-03-11
申请号：US16885499
申请日：2020-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Younghwan Son , Sanghoon Jeong , Sangjun Hong , Seogoo Kang , Jeehoon Han
IPC: H01L27/11582 , H01L27/1157 , H01L27/11565
Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.
-
公开(公告)号：US10396088B2
公开(公告)日：2019-08-27
申请号：US15696276
申请日：2017-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sohyeon Lee , Sunil Shim , Jaeduk Lee , Jaehoon Jang , Jeehoon Han
IPC: H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L23/52 , H01L23/528 , H01L21/768 , H01L23/522
Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.
-
-
-
-
-
-
-
-
-
Search Results
80
records
(took 0.032 seconds)
