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公开(公告)号：US09240238B2
公开(公告)日：2016-01-19
申请号：US14033100
申请日：2013-09-20
Applicant: SanDisk Technologies Inc.
Inventor： Deepak Raghu , Gautam Dusija , Chris Avila , Yingda Dong , Man Mui
CPC classification number: G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3427
Abstract: In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor threshold voltages cannot be returned to a desired threshold voltage range then modified program conditions, including increased back gate voltage, may be used to allow programming.
Abstract translation: 在三维NAND存储器中，背栅晶体管中增加的阈值电压可能导致程序故障，特别是在靠近后门的字线上。 当背栅极晶体管阈值电压不能返回到期望的阈值电压范围时，可以使用包括增加的背栅电压的修改的程序条件来允许编程。
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公开(公告)号：US09142324B2
公开(公告)日：2015-09-22
申请号：US14016785
申请日：2013-09-03
Applicant: SanDisk Technologies Inc.
Inventor： Deepak Raghu , Gautam Dusija , Chris Avila , Yingda Dong , Man Mui
CPC classification number: G11C29/50004 , G11C16/0483 , G11C16/10 , G11C29/44
Abstract: When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors.
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33.发明授权Selection of data for redundancy calculation in three dimensional nonvolatile memory 有权在三维非易失性存储器中选择用于冗余计算的数据公开(公告)号：US09092363B2
公开(公告)日：2015-07-28
申请号：US14281243
申请日：2014-05-19
Applicant: SanDisk Technologies Inc.
Inventor： Chris Avila , Gautam Dusija , Jian Chen , Yingda Dong , Man Mui , Seungpil Lee , Alex Mak
CPC classification number: G06F11/1068 , G06F12/0246 , G11C16/0483 , G11C16/349 , G11C29/04 , G11C29/82 , G11C2213/71
Abstract: Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block.
Abstract translation: 基于它们用于计算冗余数据的位置来选择存储在三维存储器阵列中的部分数据。 选择位置，使得给定计算的一组部分中的两个部分可能在同一时间变得不可校正。 所选择的部分可以被至少一个字线分隔开并且被块中的至少一个字符串隔开。
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Patent Agency Ranking
34.发明授权Flash memory techniques for recovering from write interrupt resulting from voltage fault 有权用于从由电压故障引起的写中断恢复的闪存技术公开(公告)号：US09037902B2
公开(公告)日：2015-05-19
申请号：US13841180
申请日：2013-03-15
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Gautam Dusija , Jianmin Huang , Chris N. Avila , Grishma S. Shah , Yi-Chieh Chen , Alexander K. Mak , Farookh Moogat
CPC classification number: G06F11/1068 , G06F11/0751 , G06F11/0754 , G06F11/1448 , G06F11/1458 , G06F11/1666
Abstract: Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.
Abstract translation: 公开了一种与具有非易失性存储器阵列（NVM）的闪速存储器件相关的技术，用于从由主机供应的存储器电压故障引起的写中断恢复。 存储器控制器被配置为在存储器电压被验证为在可接受的范围内之前控制对写入中断的发生的响应，该响应包括写入NVM，一个或多个安全副本 上页数据的第一扇区和低页数据的第二扇区的一部分的安全副本，并终止写中断。 终止写中断可能包括从主机接收新数据，同时避免向主机发送错误消息。
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公开(公告)号：US20150012802A1
公开(公告)日：2015-01-08
申请号：US14281432
申请日：2014-05-19
Applicant: SanDisk Technologies Inc.
Inventor： Chris Avila , Gautam Dusija , Jian Chen , Mrinal Kochar , Abhijeet Manohar
CPC classification number: G06F11/1072 , G06F12/0246 , G06F2212/7209 , G11C11/5628 , G11C16/3418 , G11C29/52 , G11C2029/0411 , G11C2211/5641
Abstract: Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory.
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公开(公告)号：US20140369123A1
公开(公告)日：2014-12-18
申请号：US14274440
申请日：2014-05-09
Applicant: SanDisk Technologies Inc.
Inventor： Xiying Costa , Alexander Kwok-Tung Mak , Chris Avila , Gautam Dusija , Man Mui
CPC classification number: G11C16/107 , G11C16/0408 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16
Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.
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公开(公告)号：US20140355345A1
公开(公告)日：2014-12-04
申请号：US14281404
申请日：2014-05-19
Applicant: SanDisk Technologies Inc.
Inventor： Chris Avila , Gautam Dusija , Jian Chen , Yingda Dong , Man Mui , Seungpil Lee , Alex Mak
CPC classification number: G11C16/3404 , G06F11/1048 , G06F11/141 , G06F11/1497 , G11C29/04
Abstract: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.
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38.发明申请FLASH MEMORY TECHNIQUES FOR RECOVERING FROM WRITE INTERRUPT RESULTING FROM VOLTAGE FAULT 有权用于从电压故障导致的写中断恢复的闪存存储器技术公开(公告)号：US20140281683A1
公开(公告)日：2014-09-18
申请号：US13841180
申请日：2013-03-15
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Gautam Dusija , Jianmin Huang , Chris N. Avila , Grishma S. Shah , Yi-Chieh Chen , Alexander K. Mak , Farookh Moogat
IPC: G06F11/10
CPC classification number: G06F11/1068 , G06F11/0751 , G06F11/0754 , G06F11/1448 , G06F11/1458 , G06F11/1666
Abstract: Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.
Abstract translation: 公开了一种与具有非易失性存储器阵列（NVM）的闪速存储器件相关的技术，用于从由主机供应的存储器电压故障引起的写中断恢复。 存储器控制器被配置为在存储器电压被验证为在可接受的范围内之前控制对写入中断的发生的响应，该响应包括写入NVM，一个或多个安全副本 上页数据的第一扇区和低页数据的第二扇区的一部分的安全副本，并终止写中断。 终止写中断可能包括从主机接收新数据，同时避免向主机发送错误消息。
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