中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.033 seconds)

    Group word line erase and erase-verify methods for 3D non-volatile memory
    1.
    发明授权
    Group word line erase and erase-verify methods for 3D non-volatile memory 有权
    用于3D非易失性存储器的组字线擦除和擦除验证方法

    公开(公告)号：US09047973B2

    公开(公告)日：2015-06-02

    申请号：US14273900

    申请日：2014-05-09

    Applicant: SanDisk Technologies Inc.

    Inventor： Xiying Costa ,  Alex Mak ,  Johann Alsmeier ,  Man L Mui

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/14

    CPC classification number: G11C16/3445 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11582

    Abstract: An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

    Abstract translation: 根据预期的擦除速度将存储元件分配给组的3D堆叠存储器件的擦除操作。 然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。 在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。 可以将所有组一起设置为擦除或禁止状态。 在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

    Selective Word Line Erase In 3D Non-Volatile Memory
    2.
    发明申请
    Selective Word Line Erase In 3D Non-Volatile Memory 有权
    3D非易失性存储器中的选择性字线擦除

    公开(公告)号：US20150063033A1

    公开(公告)日：2015-03-05

    申请号：US14536923

    申请日：2014-11-10

    Applicant: SanDisk Technologies Inc.

    Inventor： Yingda Dong ,  Alex Mak ,  Seungpil Lee ,  Johann Alsmeier

    IPC: G11C16/14 ,  G11C16/04

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11582 ,  H01L29/7926

    Abstract: An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

    Abstract translation: 用于3D堆叠存储器件的擦除处理允许擦除存储单元块的一部分。 在一种方法中，在U形NAND串配置中，漏极或源极侧列中的存储单元被擦除。 在另一种方法中，例如在U形或直的NAND串配置中，擦除存储器单元列的一部分中的存储单元，并且在擦除和未擦除的存储器单元之间提供虚拟存储单元。 虚拟存储器单元可以在擦除存储器单元的任一侧（例如，高于和低于），或者在未擦除的存储器单元的任一侧上。 虚拟存储单元不能存储用户数据，但是由于电容耦合，防止擦除的存储单元的阈值电压的降档改变未擦除的存储单元的阈值电压。

    Group word line erase and erase-verify methods for 3D non-volatile memory
    5.
    发明授权
    Group word line erase and erase-verify methods for 3D non-volatile memory 有权
    用于3D非易失性存储器的组字线擦除和擦除验证方法

    公开(公告)号：US09330778B2

    公开(公告)日：2016-05-03

    申请号：US14524153

    申请日：2014-10-27

    Applicant: SanDisk Technologies Inc.

    Inventor： Xiying Costa ,  Alex Mak ,  Johann Alsmeier ,  Man L Mui

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115

    CPC classification number: G11C16/3445 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11582

    Abstract: An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

    Abstract translation: 3D堆叠存储器件的擦除操作根据预期的擦除速度将存储元件分配给组。 然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。 在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。 可以将所有组一起设置为擦除或禁止状态。 在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

    Group Word Line Erase And Erase-Verify Methods For 3D Non-Volatile Memory
    8.
    发明申请
    Group Word Line Erase And Erase-Verify Methods For 3D Non-Volatile Memory 有权
    用于3D非易失性存储器的组字行擦除和擦除验证方法

    公开(公告)号：US20140247668A1

    公开(公告)日：2014-09-04

    申请号：US14273900

    申请日：2014-05-09

    Applicant: SanDisk Technologies Inc.

    Inventor： Xiying Costa ,  Alex Mak ,  Johann Alsmeier ,  Man L. Mui

    IPC: G11C16/34 ,  G11C16/14

    CPC classification number: G11C16/3445 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11582

    Abstract: An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

    Abstract translation: 根据预期的擦除速度将存储元件分配给组的3D堆叠存储器件的擦除操作。 然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。 在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。 可以将所有组一起设置为擦除或禁止状态。 在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

    GROUP WORD LINE ERASE AND ERASE-VERIFY METHODS FOR 3D NON-VOLATILE MEMORY
    9.
    发明申请
    GROUP WORD LINE ERASE AND ERASE-VERIFY METHODS FOR 3D NON-VOLATILE MEMORY 有权
    用于3D非易失性存储器的组字线删除和删除验证方法

    公开(公告)号：US20140226414A1

    公开(公告)日：2014-08-14

    申请号：US13767708

    申请日：2013-02-14

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Xiying Costa ,  Alex Mak ,  Johann Alsmeier ,  Man L. Mui

    IPC: G11C16/14

    CPC classification number: G11C16/3445 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11582

    Abstract: An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

    Abstract translation: 根据预期的擦除速度将存储元件分配给组的3D堆叠存储器件的擦除操作。 然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。 在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。 可以将所有组一起设置为擦除或禁止状态。 在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

    Selective word line erase in 3D non-volatile memory
    10.
    发明授权
    Selective word line erase in 3D non-volatile memory 有权
    3D非易失性存储器中的选择性字线擦除

    公开(公告)号：US09318206B2

    公开(公告)日：2016-04-19

    申请号：US14536923

    申请日：2014-11-10

    Applicant: SanDisk Technologies Inc.

    Inventor： Yingda Dong ,  Alex Mak ,  Seungpil Lee ,  Johann Alsmeier

    IPC: G11C16/14 ,  G11C16/04 ,  G11C16/16 ,  H01L29/792 ,  H01L27/115

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11582 ,  H01L29/7926

    Abstract: An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

    Abstract translation: 用于3D堆叠存储器件的擦除处理允许擦除存储单元块的一部分。 在一种方法中，在U形NAND串配置中，漏极或源极侧列中的存储单元被擦除。 在另一种方法中，例如在U形或直的NAND串配置中，擦除存储器单元列的一部分中的存储单元，并且在擦除和未擦除的存储器单元之间提供虚拟存储单元。 虚拟存储器单元可以在擦除存储器单元的任一侧（例如，高于和低于），或者在未擦除的存储器单元的任一侧上。 虚拟存储单元不能存储用户数据，但是由于电容耦合，防止擦除的存储单元的阈值电压的降档改变未擦除的存储单元的阈值电压。

Patent Agency Ranking