公开(公告)号：US20090283806A1

公开(公告)日：2009-11-19

申请号：US12121387

申请日：2008-05-15

Applicant: Frank Bin YANG ,  Andrew M. WAITE ,  Scott Luning

Inventor： Frank Bin YANG ,  Andrew M. WAITE ,  Scott Luning

IPC: H01L29/00 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

Abstract translation: 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US07521380B2

公开(公告)日：2009-04-21

申请号：US11738828

申请日：2007-04-23

Applicant: Andrew M. Waite ,  Scott Luning ,  Frank (Bin) Yang

Inventor： Andrew M. Waite ,  Scott Luning ,  Frank (Bin) Yang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.

Abstract translation: 提供了一种在半导体衬底上制造半导体器件的方法。 在半导体衬底上形成多个窄栅极间距晶体管（NPT）和宽栅极间距晶体管（WPT）。 NPT间隔开第一距离，并且WPT间隔开大于第一距离的第二距离。 沉积覆盖在NPT，WPT和半导体层上的第一应力衬垫层，沉积覆盖在第一应力衬垫层上的蚀刻停止层，并且沉积覆盖在蚀刻停止层上的第二应力衬垫层。 覆盖在WPT上的第二应力衬垫层的一部分被覆盖，并且去除覆盖在NPT上的第二应力衬垫层的暴露部分以露出蚀刻停止层的暴露部分。 去除覆盖在NPT上的蚀刻停止层的暴露部分。

公开(公告)号：US07279389B2

公开(公告)日：2007-10-09

申请号：US11280484

申请日：2005-11-16

Applicant: Karla Romero ,  Thorsten Kammler ,  Scott Luning ,  Hans Van Meer

Inventor： Karla Romero ,  Thorsten Kammler ,  Scott Luning ,  Hans Van Meer

IPC: H01L21/336

CPC classification number: H01L21/32139 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.

Abstract translation: 通过提供包括用于图案化栅电极结构的至少三个不同层的硬掩模层堆叠，可以实现随后的选择性外延生长工艺中复杂光刻所需的约束以及覆盖层完整性，从而提供进一步的潜力 晶体管器件的器件缩放需要高的漏极和源极区域。

公开(公告)号：US07176110B2

公开(公告)日：2007-02-13

申请号：US10862518

申请日：2004-06-07

Applicant: Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

Inventor： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L29/66628 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/665

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Abstract translation: 可以对于不同的器件区域单独地调整极限比例的半导体器件中的外延生长的半导体区域的高度，因为可以执行两个或更多个外延生长步骤，其中外延生长掩模选择性地抑制在指定器件中形成半导体区域 地区。 在其它实施例中，公共外延生长工艺可以用于两个或更多个不同的器件区域，随后可以在所选择的器件区域上执行选择性氧化工艺，以便精确地降低所选区域中先前外延生长的半导体区域的高度 。

公开(公告)号：US07144786B2

公开(公告)日：2006-12-05

申请号：US10891996

申请日：2004-07-15

Applicant: Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

Inventor： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

IPC: H01L21/336

CPC classification number: H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

Abstract: By using sidewall spacers adjacent to a gate electrode structure both as an epitaxial growth mask and an implantation mask, the complexity of a conventional process flow for forming raised drain and source regions may be significantly reduced, thereby reducing production costs and enhancing yield by lowering the defect rate.

Abstract translation: 通过使用与栅极电极结构相邻的侧壁间隔作为外延生长掩模和注入掩模，可以显着降低形成隆起的漏极和源极区域的常规工艺流程的复杂性，从而降低生产成本并通过降低 缺陷率。

公开(公告)号：US20050095820A1

公开(公告)日：2005-05-05

申请号：US10862518

申请日：2004-06-07

Applicant: Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

Inventor： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  C30B1/00 ,  H01L21/20 ,  H01L21/36

CPC classification number: H01L29/66628 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/665

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Abstract translation: 可以对于不同的器件区域单独地调整极限比例的半导体器件中的外延生长的半导体区域的高度，因为可以执行两个或更多个外延生长步骤，其中外延生长掩模选择性地抑制在指定器件中形成半导体区域 地区。 在其它实施例中，公共外延生长工艺可以用于两个或更多个不同的器件区域，随后可以在所选择的器件区域上执行选择性氧化工艺，以便精确地降低所选区域中先前外延生长的半导体区域的高度 。

公开(公告)号：US20050093075A1

公开(公告)日：2005-05-05

申请号：US10974232

申请日：2004-10-27

Applicant: Ralf Bentum ,  Scott Luning ,  Andy Wei

Inventor： Ralf Bentum ,  Scott Luning ,  Andy Wei

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L29/66628 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78687

Abstract: By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.

Abstract translation: 通过优选通过半导体层的局部氧化来凹入半导体层，可以通过随后的外延生长工艺在栅极电极结构附近的薄化半导体层中引入应力诱导材料和/或掺杂物种类。 特别地，与栅电极结构相邻形成的应力诱导材料根据所沉积材料的类型施加压缩或拉伸应力，从而也增强了晶体管元件的沟道区中电荷载流子的迁移率。

公开(公告)号：US20050009285A1

公开(公告)日：2005-01-13

申请号：US10915638

申请日：2004-08-09

Applicant: Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

Inventor： Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S257/90

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract translation: 一种具有降低的栅极电阻的绝缘栅极半导体器件（100）和用于制造半导体器件（100）的方法。 栅极结构（112）形成在半导体衬底（102）的主表面（104）上。 在栅极结构（112）的侧壁附近形成连续的氮化物间隔物（118,128）。 使用单个蚀刻来蚀刻和凹入氮化物间隔物（118,128）以暴露栅极结构（112）的上部（115A，117A）。 源极（132）和漏极（134）区域形成在半导体衬底（102）中。 在栅极结构（112）和源极区（132）和漏极区（134）的顶表面（109）和暴露的上部（115A，117A）上形成硅化物区域（140,142,144）。 电极（150,152,154）形成为与相应的栅极结构（112），源极区（132）和漏极区（134）的硅化物（140,142,144）接触。

公开(公告)号：US5639691A

公开(公告)日：1997-06-17

申请号：US590781

申请日：1996-01-24

Applicant: Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/283

CPC classification number: H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

公开(公告)号：US5626967A

公开(公告)日：1997-05-06

申请号：US452589

申请日：1995-05-25

Applicant: Shekhar Pramanick ,  Scott Luning ,  Jonathon Fewkes

Inventor： Shekhar Pramanick ,  Scott Luning ,  Jonathon Fewkes

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  H01L29/06

CPC classification number: G03F7/091 ,  H01L21/0276 ,  H01L21/32137

Abstract: A structure for patterning a polysilicon layer includes a TiN layer located above an amorphous silicon (a-Si) layer forming a TiN/a-Si stack. The TiN/a-Si stack is located above the polysilicon layer. The TiN layer serves as an ARC to reduce overexposure of the photoresist used to pattern the polysilicon layer, while the a-Si layer prevents contamination of the layer below the polysilicon layer.

Abstract translation: 用于图案化多晶硅层的结构包括位于形成TiN / a-Si叠层的非晶硅（a-Si）层之上的TiN层。 TiN / a-Si堆叠位于多晶硅层上方。 TiN层用作ARC以减少用于图案化多晶硅层的光刻胶的过度曝光，而a-Si层防止多晶硅层下面的层的污染。