公开(公告)号：US5639691A

公开(公告)日：1997-06-17

申请号：US590781

申请日：1996-01-24

申请人： Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

发明人： Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC分类号： H01L21/768 ,  H01L21/283

CPC分类号： H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

公开(公告)号：US5990557A

公开(公告)日：1999-11-23

申请号：US964430

申请日：1997-11-04

申请人： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

发明人： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485

CPC分类号： H01L21/02164 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/7682 ,  H01L21/76837 ,  H01L23/5222 ,  H01L2924/0002

摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with void free insulating material with a dielectric constant of greater than about 3.5.

摘要翻译： 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别通过沉积具有差的绝缘材料的步进功能的非共形源（例如硅烷）而具有约0.5微米或更小的间隙 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后 间隙，沉积的非共形材料与沉积同时或顺序蚀刻，以用无空隙绝缘填充剩余的间隙。 沉积的绝缘材料的表面被平坦化为所需的厚度。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或 较低，并且所有剩余的间隙都填充有绝缘材料，介电常数大于约3.5。

公开(公告)号：US5691573A

公开(公告)日：1997-11-25

申请号：US481030

申请日：1995-06-07

申请人： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein

发明人： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L23/52

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

摘要翻译： 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在所有导电线都已经接收到保形膜 绝缘材料和可流动的绝缘材料，优选通过蚀刻从具有约0.5微米或更小的间隙的那对导电线去除复合绝缘材料。 现在，沉积具有差的阶梯函数的非共形绝缘材料，并且在0.5微米或更小的开放间隙中产生大的空隙。 在形成空隙之后，沉积继续并且在所需的绝缘复合厚度下被平坦化。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所得到的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，导电线对之间的绝缘介电常数为0.5或更小的间隙，与空隙结合为至少约3 或更低，并且所有剩余间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

公开(公告)号：US5776834A

公开(公告)日：1998-07-07

申请号：US478315

申请日：1995-06-07

申请人： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

发明人： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/471

CPC分类号： H01L21/02164 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/7682 ,  H01L21/76837 ,  H01L23/5222 ,  H01L2924/0002

摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with void free insulating material with a dielectric constant of greater than about 3.5.

公开(公告)号：US07071564B1

公开(公告)日：2006-07-04

申请号：US10791904

申请日：2004-03-04

申请人： Darrell M. Erb ,  Steven Avanzino ,  Christy Mei-Chu Woo

发明人： Darrell M. Erb ,  Steven Avanzino ,  Christy Mei-Chu Woo

IPC分类号： H01L29/40 ,  H01L23/12

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： The electromigration and stress migration of Cu interconnects is significantly reduced by forming a composite capping layer comprising a layer of β-Ta on the upper surface of the inlaid Cu, a layer of tantalum nitride on the β-Ta layer and a layer of α-Ta on the tantalum nitride layer. Embodiments include forming a recess in an upper surface of Cu inlaid in a dielectric layer, depositing a layer of β-Ta at a thickness of 25 Å to 40 Å, depositing a layer of tantalum nitride at a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å. Embodiments further include forming an overlying dielectric layer, forming an opening therein, e.g., a via opening or a dual damascene opening, lining the opening with α-Ta, and filling the opening with Cu in electrical contact with the underlying inlaid Cu.

摘要翻译： 通过在嵌入的Cu的上表面上形成包含β-Ta层的复合顶盖层，β-Ta层上的氮化钽层和α-Ta层的一层复合覆盖层，显着降低了铜互连的电迁移和应力迁移， Ta在氮化钽层上。 实施例包括在介电层中嵌入的Cu的上表面中形成凹陷，沉积厚度为的Å-Ta层，沉积厚度为Å至100埃的氮化钽层，以及 然后沉积厚度为200埃至500埃的α-Ta层。 实施例还包括形成覆盖的介电层，在其中形成开口，例如通孔开口或双镶嵌开口，用α-Ta衬套开口，以及用与电镀底层Cu接触的Cu填充开口。

公开(公告)号：US07157795B1

公开(公告)日：2007-01-02

申请号：US10934511

申请日：2004-09-07

申请人： Darrell M. Erb ,  Steven C. Avanzino ,  Christy Mei-Chu Woo

发明人： Darrell M. Erb ,  Steven C. Avanzino ,  Christy Mei-Chu Woo

IPC分类号： H01L23/48

CPC分类号： H01L21/2855 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  Y10S438/927

摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.

摘要翻译： 通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。 实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。

公开(公告)号：US06727592B1

公开(公告)日：2004-04-27

申请号：US10079515

申请日：2002-02-22

申请人： Christy Mei-Chu Woo ,  John E. Sanchez ,  Darrell M. Erb ,  Amit P. Marathe

发明人： Christy Mei-Chu Woo ,  John E. Sanchez ,  Darrell M. Erb ,  Amit P. Marathe

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76868 ,  H01L21/76871 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.

摘要翻译： Cu互连，例如 通过在开口中沉积阻挡层通过CVD沉积形成具有改善的电迁移阻力并通过链产量增加的双镶嵌结构，通过PVD沉积α-Ta的闪光层，厚度小于30埃 阻挡层，沉积种子层，然后用Cu填充开口。 实施方案包括沉积厚度小于的薄的α-Ta层和/或沉积在开口侧面上的原子簇的不连续区域。

公开(公告)号：US06454916B1

公开(公告)日：2002-09-24

申请号：US09477810

申请日：2000-01-05

申请人： Fei Wang ,  Steven C. Avanzino ,  Darrell M. Erb

发明人： Fei Wang ,  Steven C. Avanzino ,  Darrell M. Erb

IPC分类号： C25D1700

CPC分类号： C25D5/22 ,  B23H5/08 ,  C25D7/12 ,  C25D17/001

摘要： A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.

摘要翻译： 沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。 扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。 电镀材料填充图案化到半导体晶片的衬底中的凹槽，但是由于扩散器的接触和旋转，防止了在半导体晶片的顶表面上形成很大程度。 由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上，所以化学机械抛光（CMP）平面化被显着地减少或完全消除。

公开(公告)号：US06169034A

公开(公告)日：2001-01-02

申请号：US09199352

申请日：1998-11-25

申请人： Steven C. Avanzino ,  Darrell M. Erb ,  Diana M. Schonauer ,  Kai Yang

发明人： Steven C. Avanzino ,  Darrell M. Erb ,  Diana M. Schonauer ,  Kai Yang

IPC分类号： H01L21461

CPC分类号： H01L21/3212 ,  C09G1/02 ,  C09K3/1463

摘要： Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of soft mineral particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing magnesium oxide particles and removing any residual magnesium oxide particles after CMP with an organic acid, such as citric acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, phosphoric, boric or fluoboric acid.

摘要翻译： 在CMP期间对Cu金属化的磨损降低，并且通过使用含有在稀酸中具有高溶解度的软矿物颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。 实施方案包括用含有氧化镁颗粒的浆料进行CMP Cu金属化，并在CMP之后用有机酸如柠檬酸或乙酸或稀无机酸如盐酸，磷酸，硼酸或氟硼酸除去残留的氧化镁颗粒 。

公开(公告)号：US4745454A

公开(公告)日：1988-05-17

申请号：US926600

申请日：1986-11-03

申请人： Darrell M. Erb

发明人： Darrell M. Erb

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/1085 ,  H01L27/10805

摘要： The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region. One way of diffusing the second polarity dopant to a lesser degree than the first polarity dopant in the substrate is to select a first polarity dopant which has a diffusivity greater than the second polarity dopant. Another way of achieving the desired diffusion of first polarity dopant with respect to the second polarity dopant is to select the two dopants with diffusivities approximately equal and to diffuse the first polarity dopant before the second polarity dopants is implanted into the semiconductor substrate.

摘要翻译： 本发明提供一种在动态RAM中用于存储单元的半导体衬底中的电荷存储区域的制造方法，包括在衬底上形成绝缘层，在绝缘层上形成掩模层，形成至少一个孔 掩模层，限定半导体衬底中的电荷存储区域的孔，通过孔径注入第一极性的掺杂离子以通过衬底扩散，以及通过孔径注入第二极性的掺杂剂离子，以通过衬底扩散到 比第一极性掺杂剂扩散程度小，使得第一极性掺杂剂相对于第二极性掺杂剂的扩散的扩散形成基本上与掩模层孔的边缘对准的PN结，以限定电荷存储区域的周边 。 将第二极性掺杂剂扩散到比衬底中的第一极性掺杂剂更小程度的一种方法是选择具有大于第二极性掺杂剂的扩散率的第一极性掺杂剂。 实现第一极性掺杂剂相对于第二极性掺杂剂的期望扩散的另一种方法是选择具有大致相等的扩散率的两种掺杂剂，并且在将第二极性掺杂剂注入到半导体衬底之前扩散第一极性掺杂剂。