公开(公告)号：US06578949B2

公开(公告)日：2003-06-17

申请号：US09950716

申请日：2001-09-13

申请人： Masaru Takahashi ,  Hitoshi Hayakawa ,  Kojiro IIzuka ,  Mitsugu Ota ,  Takashi Akase ,  Hideki Okumura

发明人： Masaru Takahashi ,  Hitoshi Hayakawa ,  Kojiro IIzuka ,  Mitsugu Ota ,  Takashi Akase ,  Hideki Okumura

IPC分类号： B41J2165

CPC分类号： B41J2/16547 ,  B41J2/16526 ,  B41J2/16532

摘要： A cap member (10) which is brought into contact with a nozzle forming surface of a recording head (15) to seal up the nozzle forming surface, and a wiping member (11) which may be brought into sliding contact with the nozzle forming surface of the recording head (15) are disposed on a cap holder (31). With progress of a cleaning operation in which ink is placed under a negative pressure, and sucked and discharged from the recording head, a cap retaining member (50) is moved upward and placed to a set state, whereby blocking the slanting and downward movement of the cap member (10). Then, the wiping member (11) located on the cap holder (31) slides on the nozzle forming surface to wipe the nozzle forming surface. To a flushing operation, the cap retaining member (50) is moved downward and placed to a reset state. In this state, the wiping member (11) does not slide on the nozzle forming surface.

公开(公告)号：US06265744B1

公开(公告)日：2001-07-24

申请号：US09304342

申请日：1999-05-04

申请人： Hideki Okumura

发明人： Hideki Okumura

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811

摘要： An electronic field reduction in a corner of a trench section of a semiconductor is achieved by forming a p-type base region in a source area of an n-type drain region, and both an n-type source region and a gate leading region are formed in a surface area of the p-type base region separately from each other. A trench section is formed in both the source region and gate leading region to reach the drain region. Polysilicon is formed in the trench section and on the surface of a semiconductor substrate with a gate insulation film interposed therebetween and then thermally treated. An interlayer insulation film is deposited on the entire surface of the semiconductor substrate, and then contact holes reaching the gate leading region and the source and base regions in the peripheral portion of the trench section in the source region are formed. A source/base electrode which contacts both the source and base regions through one of the contact holes is formed. A gate electrode is formed which contacts both the gate leading region and the polysilicon in the trench through the other contact hole.

摘要翻译： 通过在n型漏极区域的源区域中形成p型基极区域，并且n型源极区域和栅极引出区域都是在半导体的沟槽部分的拐角处的电场减小 形成在p型基底区域的表面区域中。 在源极区域和栅极引出区域中形成沟槽部分以到达漏极区域。 在沟槽部分和半导体衬底的表面上形成多晶硅，并在其间插入栅极绝缘膜，然后进行热处理。 在半导体衬底的整个表面上沉积层间绝缘膜，然后形成到达栅极引导区域的接触孔，并且形成源极区域中的沟槽部分的周边部分中的源极和基极区域。 形成通过一个接触孔接触源极和基极区域的源/底电极。 形成栅极电极，其通过另一个接触孔与沟槽中的栅极引出区域和多晶硅接触。

公开(公告)号：US5811179A

公开(公告)日：1998-09-22

申请号：US554281

申请日：1995-11-06

申请人： Kazunori Sakamoto ,  Hideo Hatanaka ,  Yasuhiro Ueyama ,  Kiyoshi Kobata ,  Kazunori Kubota ,  Hideki Okumura

发明人： Kazunori Sakamoto ,  Hideo Hatanaka ,  Yasuhiro Ueyama ,  Kiyoshi Kobata ,  Kazunori Kubota ,  Hideki Okumura

IPC分类号： G11B5/708

CPC分类号： G11B5/708 ,  Y10S428/90 ,  Y10T428/25 ,  Y10T428/256 ,  Y10T428/257 ,  Y10T428/26

摘要： A magnetic recording medium including a non-magnetic polymeric support and a magnetic layer on the non-magnetic polymeric support. The magnetic layer is positioned to be in contact with a record/playback head and includes ferromagnetic powder, abrasive material and binder resin, with at least 40 parts by weight of the abrasive material per 100 parts by weight of the ferromagnetic powder. The ferromagnetic powder has a saturation magnetization .sigma.s of 80 emu/g or more and long axis length of 0.25 .mu.m or less.

摘要翻译： 包括非磁性聚合物载体和在非磁性聚合物载体上的磁性层的磁记录介质。 磁性层定位成与记录/回放头接触，并且包括铁磁粉末，研磨材料和粘合剂树脂，每100重量份铁磁粉末至少40重量份的研磨材料。 铁磁粉末的饱和磁化σs为80emu / g以上，长轴长度为0.25μm以下。

公开(公告)号：US08890237B2

公开(公告)日：2014-11-18

申请号：US13419396

申请日：2012-03-13

申请人： Takahiro Kawano ,  Hideki Okumura

发明人： Takahiro Kawano ,  Hideki Okumura

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L23/48

CPC分类号： H01L23/48 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device according to one embodiment includes a first electrode, a semiconductor substrate provided on the first electrode, and an insulating member. A terminal trench is made in the upper surface of the semiconductor substrate in a region including a boundary between a cell region and a terminal region. The semiconductor substrate includes a first portion of a first conductivity type and connected to the first electrode, a second portion of the first conductivity type, a third portion of a second conductivity type provided on the second portion in the cell region and connected to the second electrode, and a fourth portion of the first conductivity type selectively provided on the third portion and connected to the second electrode. The insulating member is disposed between the third portion and the second portion in a direction from the cell region toward the terminal region.

摘要翻译： 根据一个实施例的功率半导体器件包括第一电极，设置在第一电极上的半导体衬底和绝缘构件。 在包括单元区域和端子区域之间的边界的区域中，在半导体衬底的上表面中形成端子沟槽。 半导体衬底包括第一导电类型的第一部分并连接到第一电极，第一导电类型的第二部分，第二导电类型的第三部分，设置在电池区域的第二部分上，并连接到第二导电类型的第二部分 电极，以及选择性地设置在第三部分上并连接到第二电极的第一导电类型的第四部分。 绝缘构件在从单元区域朝向端子区域的方向上配置在第三部分和第二部分之间。

公开(公告)号：US20130153995A1

公开(公告)日：2013-06-20

申请号：US13607449

申请日：2012-09-07

申请人： Hiroto MISAWA ,  Hideki Okumura

发明人： Hiroto MISAWA ,  Hideki Okumura

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7397

摘要： A semiconductor device includes a first region with second conductivity type formed over a semiconductor layer with first conductivity type. On this first region, the second region of the first conductivity type is selectively provided. On the same first region, a third region of second conductivity type is also selectively provided and is adjoined to the second region. The first control electrode is provided within a trench located deeper than the first side of the second region compared to the first region. The first control electrode includes a part opposed to the first and second regions separated by a first insulator, and a second part opposed to the semiconductor layer separated by a thicker second insulator. Inside the trench, the second control electrode is provided between the trench bottom and the first control electrode. The second control electrode is opposed to the semiconductor layer through a third insulator.

摘要翻译： 半导体器件包括在具有第一导电类型的半导体层上形成的具有第二导电类型的第一区域。 在该第一区域上，选择性地提供第一导电类型的第二区域。 在相同的第一区域上，也选择性地提供第二导电类型的第三区域并与第二区域邻接。 与第一区域相比，第一控制电极设置在比第二区域的第一侧更深的沟槽内。 第一控制电极包括与由第一绝缘体隔开的第一和第二区域相对的部分，以及与较厚的第二绝缘体隔开的与半导体层相对的第二部分。 在沟槽内，第二控制电极设置在沟槽底部和第一控制电极之间。 第二控制电极通过第三绝缘体与半导体层相对。

公开(公告)号：US07596994B2

公开(公告)日：2009-10-06

申请号：US11579942

申请日：2005-11-09

申请人： Tsuguo Koguchi ,  Hideki Okumura

发明人： Tsuguo Koguchi ,  Hideki Okumura

IPC分类号： G01M15/02

CPC分类号： G01B5/003 ,  F16C7/023 ,  F16C9/045 ,  G01B11/024

摘要： A connecting rod inspecting device is provided with a work table for placing a connecting rod in a status where the connecting rod is positioned at a prescribed position; a slide unit for reciprocating the work table along the horizontal direction; and first to fourth distance sensors for measuring a step quantity (D) of a step part by irradiating measuring planes composed of curved surfaces with laser beams and measuring distances between the sensors and the planes irradiated with the beams. Conforming/nonconforming judgment is made by the measured step quantity (D) and a range of allowable quantities previously set.

摘要翻译： 连杆检查装置设置有用于将连杆放置在连杆位于规定位置的状态的工作台; 滑动单元，用于沿着水平方向使工作台往复运动; 以及第一至第四距离传感器，用于通过用激光束照射由曲面组成的测量平面并测量传感器与照射的平面之间的距离来测量台阶部分的步数（D）。 通过测量的步数（D）和先前设置的允许量的范围来进行符合/不一致判断。

公开(公告)号：US20060145290A1

公开(公告)日：2006-07-06

申请号：US11294411

申请日：2005-12-06

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/00 ,  H01L21/425 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

公开(公告)号：US06995426B2

公开(公告)日：2006-02-07

申请号：US10327937

申请日：2002-12-26

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体层中的扩散区域。 扩散区域分别包括第一和第二导电类型的第一和第二杂质扩散区域。 扩散区域具有由第一和第二杂质扩散区域的杂质浓度限定的第一和第二区域。 第一和第二区域之间的结点形成在第一和第二杂质扩散区域彼此重叠的部分中。 在第一或第二区域的半导体层的平面方向上的杂质浓度的周期小于半导体层的平面方向上的构成第一或第二区域的第一和第二杂质扩散区域的最大宽度 第二区。

公开(公告)号：US20050253190A1

公开(公告)日：2005-11-17

申请号：US11101570

申请日：2005-04-08

申请人： Hideki Okumura ,  Mitsuhiko Kitagawa ,  Takuma Hara ,  Takayoshi Ino ,  Kiyotaka Arai ,  Satoshi Taji ,  Masanobu Tsuchitani

发明人： Hideki Okumura ,  Mitsuhiko Kitagawa ,  Takuma Hara ,  Takayoshi Ino ,  Kiyotaka Arai ,  Satoshi Taji ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42368

摘要： A semiconductor device comprises a semiconductor substrate; a semiconductor layer provided on the surface of the semiconductor substrate; a base layer provided on the surface of the semiconductor layer; a source layer provided on the surface of the base layer; a trench formed to pass through the source layer, the base layer, and the semiconductor layer from the surface of the source layer, and reaching the semiconductor substrate; a gate electrode provided from the source layer to at least the semiconductor layer within the trench; and an insulator provided between the gate electrode and the base layer so as to fill in the inside of the trench below the gate electrode, the insulator insulating the gate electrode from the base layer, and generating a potential distribution from the gate electrode toward the semiconductor substrate when a voltage is applied to the gate electrode.

摘要翻译： 半导体器件包括半导体衬底; 设置在所述半导体衬底的表面上的半导体层; 设置在所述半导体层的表面上的基底层; 源层，设置在基层的表面上; 形成为从源极层的表面通过源极层，基极层和半导体层并到达半导体基板的沟槽; 从所述源极层至所述沟槽内的所述半导体层设置的栅电极; 以及设置在所述栅电极和所述基极层之间的绝缘体，以便填充所述栅电极下方的所述沟槽的内部，所述绝缘体将所述栅电极与所述基极层绝缘，并且从所述栅电极向所述半导体产生电势分布 衬底，当电压施加到栅电极时。

公开(公告)号：US5701225A

公开(公告)日：1997-12-23

申请号：US467823

申请日：1995-06-06

申请人： Hideki Okumura ,  Kazunori Sakamoto ,  Kiyoshi Kobata ,  Kazunori Kubota

发明人： Hideki Okumura ,  Kazunori Sakamoto ,  Kiyoshi Kobata ,  Kazunori Kubota

IPC分类号： G11B23/087 ,  G11B5/024 ,  G11B23/26 ,  G11B23/20

CPC分类号： G11B23/26

摘要： A tape cassette has a pair of reels each including a reel hub, with each hub having an anchor groove defined in an outer peripheral surface thereof so as to extend in a lengthwise direction thereof. A generally elongated clamping piece is received within the anchor groove and has a predetermined width as measured circumferentially of the reel hub. A tape medium includes a length of magnetic recording tape having opposite ends, and a leader tape connected with each of the opposite ends of the length of magnetic recording tape by of a splicing tape of a predetermined length. One end of the leader tape remote from the length of magnetic recording tape is received within the reel hub and anchored to the reel hub with the clamping piece snapped into the anchor groove. The splicing tape is, when the tape medium is wound around the reel hub, positioned immediately radially outwardly of and encompassing the predetermined width of the clamping piece.

摘要翻译： 磁带盒具有一对卷轴，每一个卷盘均包括卷盘毂，每个轮毂在其外圆周表面上具有一定位于其长度方向上的锚定槽。 通常细长的夹紧件容纳在锚定槽内并且具有沿卷轴毂周向测量的预定宽度。 磁带介质包括具有相对端的长度的磁记录带，以及通过预定长度的拼接带与磁记录带的长度的每个相对端连接的引带。 远离磁记录带长度的引导带的一端被接收在卷轴轮毂内并且被夹紧在锚定槽中并且锚固到卷轴毂上。 当磁带介质卷绕在卷盘毂上时，拼接胶带位于夹紧片的预定宽度的径向外侧并且包围预定宽度的位置。