公开(公告)号：US20220336020A1

公开(公告)日：2022-10-20

申请号：US17850447

申请日：2022-06-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Steven Lemke ,  Hieu Van Tran ,  Yuri Tkachev ,  Louisa Schneider ,  Henry A. Om'mani ,  Thuan Vu ,  Nhan Do ,  Vipin Tiwari

IPC: G11C16/10 ,  G06N3/063 ,  G11C16/26 ,  G11C16/14

Abstract: Examples for ultra-precise tuning of a selected memory cell are disclosed. In one example, a method of programming a first memory cell in a neural memory to a target value is disclosed, the method comprising programming a second memory cell by applying programming voltages to terminals of the second memory cell; and determining if an output of the first memory cell has reached the target value.

公开(公告)号：US11423979B2

公开(公告)日：2022-08-23

申请号：US16503355

申请日：2019-07-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

IPC: G11C11/56 ,  G11C11/16 ,  G06N3/06 ,  G11C11/4074 ,  G06F17/16

Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.

公开(公告)号：US20220215239A1

公开(公告)日：2022-07-07

申请号：US17219352

申请日：2021-03-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Nghia Le ,  Toan Le ,  Hien Pham

IPC: G06N3/063 ,  G11C16/10 ,  G11C16/34 ,  G06F7/523 ,  H03M1/38

Abstract: Numerous embodiments for reading or verifying a value stored in a selected non-volatile memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise various designs of input blocks for applying inputs to the VMM array during a read or verify operation and various designs of output blocks for receiving outputs from the VMM array during the read or verify operation.

公开(公告)号：US20210264983A1

公开(公告)日：2021-08-26

申请号：US16985147

申请日：2020-08-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Steven Lemke ,  Hieu Van Tran ,  Yuri Tkachev ,  Louisa Schneider ,  Henry A. Om'Mani ,  Thuan Vu ,  Nhan Do ,  Vipin Tiwari

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06N3/063

Abstract: Embodiments for ultra-precise tuning of a selected memory cell are disclosed. The selected memory cell optionally is first programmed using coarse programming and fine programming methods. The selected memory cell then undergoes ultra-precise programming through the programming of an adjacent memory cell. As the adjacent memory cell is programmed, capacitive coupling between the floating gate of the adjacent memory cell and the floating gate of the selected memory cell will cause the voltage of the floating gate of the selected memory cell to increase, but in smaller increments than could be achieved by programming the selected memory cell directly. In this manner, the selected memory cell can be programmed with ultra-precise gradations.

公开(公告)号：US20210241839A1

公开(公告)日：2021-08-05

申请号：US17239397

申请日：2021-04-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US20200272886A1

公开(公告)日：2020-08-27

申请号：US16746837

申请日：2020-01-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/063 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/14 ,  G11C16/30 ,  G11C16/08

Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. In one embodiment, the analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication systems, each vector-by-matrix multiplication system comprising an array of memory cells, a low voltage row decoder, a high voltage row decoder, and a low voltage column decoder; a plurality of output blocks, each output block providing an output in response to at least one of the plurality of vector-by-matrix multiplication systems; and a shared verify block configured to concurrently perform a verify operation after a program operation on two or more of the plurality of vector-by-matrix systems.

公开(公告)号：US20200051635A1

公开(公告)日：2020-02-13

申请号：US16550248

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20190286976A1

公开(公告)日：2019-09-19

申请号：US15991890

申请日：2018-05-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han TRan

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

公开(公告)号：US10283206B2

公开(公告)日：2019-05-07

申请号：US15792590

申请日：2017-10-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Vipin Tiwari

IPC: G11C16/28 ,  G11C16/06 ,  H01L27/11519 ,  G11C16/24 ,  G11C16/00 ,  G11C7/06 ,  G11C7/12 ,  G11C16/26

Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.

公开(公告)号：US20190080754A1

公开(公告)日：2019-03-14

申请号：US16119416

申请日：2018-08-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Numerous embodiments of methods for writing to a resistive random access memory (RRAM) cell are disclosed. In one embodiment, the system verifies if a current through the RRAM cell exceeds a threshold value, and if it does not, the system executes a concurrent write-while-verify operation. In another embodiment, the system verifies if current through the RRAM cell has reached a target value, and if it has not, the system executes a write operation and then verifies the write operation using a current comparison.