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公开(公告)号：US08281079B2
公开(公告)日：2012-10-02
申请号：US10756535
申请日：2004-01-13
IPC分类号： G06F13/42
CPC分类号： G06F9/383 , G06F9/3842 , G06F9/3861 , G06F12/0815 , G06F12/0862 , G06F2212/507 , G06F2212/6022
摘要： Multi-processor systems and methods are disclosed that employ a pre-fetch buffer to provide data fills to a source processor in response to a request. A pre-fetch buffer retrieves data as a uncached data fill. The source processor processes the data in response to a source request.
摘要翻译： 公开了多处理器系统和方法，其采用预取缓冲器来响应于请求向源处理器提供数据填充。 预取缓冲区将数据作为未缓存的数据填充检索。 源处理器响应于源请求处理数据。
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公开(公告)号：US07962696B2
公开(公告)日：2011-06-14
申请号：US10758368
申请日：2004-01-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： Systems and methods are disclosed for updating owner predictor structures. In one embodiment, a multi-processor system includes an owner predictor control that provides an ownership update message corresponding to a block of data to at least one of a plurality of owner predictors in response to a change in an ownership state of the block of data. The update message comprises an address tag associated with the block of data and an identification associated with an owner node of the block of data.
摘要翻译： 公开了用于更新所有者预测器结构的系统和方法。 在一个实施例中，多处理器系统包括所有者预测器控制，其响应于所述数据块的所有权状态的改变，将对应于数据块的所有权更新消息提供给多个所有者预测器中的至少一个 。 更新消息包括与数据块相关联的地址标签和与该数据块的所有者节点相关联的标识。
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公开(公告)号：US07409500B2
公开(公告)日：2008-08-05
申请号：US10755938
申请日：2004-01-13
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/3834 , G06F9/3842 , G06F9/3863 , G06F12/0815 , G06F2212/6022
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative data fills that are provided in response to source requests. The multi-processor system may comprise a first cache that retains cache data associated with program instructions employing data from speculative data fills, and a second cache that retains cache data associated with data from speculative data fills that have been determined to be coherent.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括具有处理器的多处理器系统，该处理器具有处理器流水线，该处理器流水线通过响应于源请求而提供的来自投机数据填充的数据执行程序指令。 多处理器系统可以包括第一高速缓存，其保存与使用来自推测数据填充的数据的程序指令相关联的高速缓存数据，以及第二高速缓存，其保存与已经被确定为相干的来自推测数据填充的数据相关联的高速缓存数据。
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公开(公告)号：US07240165B2
公开(公告)日：2007-07-03
申请号：US10758473
申请日：2004-01-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： A multi-processor system includes a requesting node that provides a first request for data to a home node. The requesting node being operative to provide a second request for the data to at least one predicted node in parallel with first request. The requesting node receives at least one coherent copy of the data from at least one of the home node and the at least one predicted node.
摘要翻译： 多处理器系统包括向家庭节点提供数据的第一请求的请求节点。 请求节点可操作以向第一请求并行地向至少一个预测节点提供数据的第二请求。 请求节点从家庭节点和至少一个预测节点中的至少一个接收数据的至少一个相干副本。
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公开(公告)号：US09588889B2
公开(公告)日：2017-03-07
申请号：US13995991
申请日：2011-12-29
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F13/00
摘要： Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories. Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.
摘要翻译： 通过读/写与缓存标签目录中的标签条目相关联的域状态字段来有效地维持高速缓存一致性的方法和装置。 可以将值分配给缓存标签目录中的标签条目的域状态字段。 缓存标签目录可能属于高速缓存标签目录的层次结构。 每个标签条目可以与来自属于第一域的高速缓存行相关联。 第一个域可能包含多个缓存。 域状态字段的值可以指示其相关联的高速缓存行是否可以被读取或改变。
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公开(公告)号：US09201792B2
公开(公告)日：2015-12-01
申请号：US13996012
申请日：2011-12-29
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译： 多核处理装置可以提供高速缓存探针和数据检索方法。 该方法可以包括将请求者的存储器请求发送到记录保存结构。 存储器请求可以具有存储请求的数据的存储器的存储器地址。 该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。 本地最后一个访问者可能在请求者所属的本地域内。 该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。
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公开(公告)号：US08438335B2
公开(公告)日：2013-05-07
申请号：US12892476
申请日：2010-09-28
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F2212/507
摘要： An apparatus to resolve cache coherency is presented. In one embodiment, the apparatus includes a microprocessor comprising one or more processing cores. The apparatus also includes a probe speculative address file unit, coupled to a cache memory, comprising a plurality of entries. Each entry includes a timer and a tag associated with a memory line. The apparatus further includes control logic to determine whether to service an incoming probe based at least in part on a timer value.
摘要翻译： 提出了一种解决高速缓存一致性的设备。 在一个实施例中，该装置包括具有一个或多个处理核心的微处理器。 该装置还包括耦合到高速缓冲存储器的探测推测地址文件单元，包括多个条目。 每个条目包括定时器和与存储器线相关联的标签。 该装置还包括至少部分地基于定时器值来确定是否对入站探测器进行服务的控制逻辑。
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公开(公告)号：US08407421B2
公开(公告)日：2013-03-26
申请号：US12639214
申请日：2009-12-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译： 这里描述了用于智能地溢出高速缓存行的装置和方法。 了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。 此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。 高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。 因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。
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39.发明授权High performance recoverable communication method and apparatus for write-only networks 失效用于只写网络的高性能可恢复通信方法和装置
公开(公告)号：US6049889A
公开(公告)日：2000-04-11
申请号：US6115
申请日：1998-01-13
摘要： A multi-node computer network includes a plurality of nodes coupled together via a data link. Each of the nodes includes a local memory, which further comprises a shared memory. Certain items of data that are to be shared by the nodes are stored in the shared portion of memory. Associated with each of the shared data items is a data structure. When a node sharing data with other nodes in the system seeks to modify the data, it transmits the modifications over the data link to the other nodes in the network. Each update is received in order by each node in the cluster. As part of the last transmission by the modifying node, an acknowledgement request is sent to the receiving nodes in the cluster. Each node that receives the acknowledgment request returns an acknowledgement to the sending node. The returned acknowledgement is written to the data structure associated with the shared data item. If there is an error during the transmission of the message, the receiving node does not transmit an acknowledgement, and the sending node is thereby notified that an error has occurred.
摘要翻译： 多节点计算机网络包括通过数据链路耦合在一起的多个节点。 每个节点包括本地存储器，其还包括共享存储器。 要由节点共享的某些数据项存储在存储器的共享部分中。 与每个共享数据项相关联的是数据结构。 当与系统中的其他节点共享数据的节点寻求修改数据时，它将数据链路上的修改发送到网络中的其他节点。 群集中的每个节点按顺序接收每个更新。 作为修改节点的最后一次传输的一部分，向群集中的接收节点发送确认请求。 接收确认请求的每个节点向发送节点返回确认。 返回的确认被写入与共享数据项相关联的数据结构。 如果在消息的发送期间存在错误，则接收节点不发送确认，并且由此通知发送节点发生了错误。
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公开(公告)号：US5509135A
公开(公告)日：1996-04-16
申请号：US951623
申请日：1992-09-25
申请人： Simon C. Steely, Jr.
发明人： Simon C. Steely, Jr.
CPC分类号： G06F12/0864
摘要： A plurality of indexes are provided for a multi-way set-associate cache of a computer system. The cache is organized as a plurality of blocks for storing data which are a copies of main memory data. Each block has an associated tag for uniquely identifying the block. The blocks and the tags are addressed by indexes. The indexes are generated by a Boolean hashing function which converts a memory address to cache indexes by combining the bits of the memory address using an exclusive OR function. Different combination of bits are used to generate a plurality of different indexes to address the tags and the associated blocks to transfer data between the cache and the central processing unit of the computer system.
摘要翻译： 为计算机系统的多路集合相关缓存提供多个索引。 高速缓存被组织为用于存储作为主存储器数据的副本的数据的多个块。 每个块都具有用于唯一标识块的关联标签。 块和标签由索引寻址。 索引由布尔散列函数生成，该函数通过使用异或函数组合存储器地址的位来将存储器地址转换为缓存索引。 使用不同的比特组合来生成多个不同的索引以寻址标签和相关联的块以在计算机系统的高速缓存和中央处理单元之间传送数据。
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