摘要:
An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
摘要:
A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
摘要:
A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
摘要:
A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.
摘要:
A level shifting device comprises an input stage, a cascode stage, a cross-coupled stage, and an output stage. The input stage may receive a data signal or binary logic input in a first data range, a complement of the data signal, and a first voltage. The cascode stage may receive a first voltage and may be connected to the input stage. The cross-coupled stage may be adapted to isolate the first voltage and may be connected to the cascode stage. The output stage may receive a second voltage, provide an output, and be connected to the cross-coupled stage. The cascode stage may be adapted to provide the first voltage as the output when the logic input is a first value and provide the second voltage as the output when the logic input is a second value. Other embodiments are also claimed and described.
摘要:
A bias generator unit is provided that includes a central bias generator to provide a bias voltage, a local bias generator to receive the bias voltage and a reference voltage and to provide a forward body bias signal or a reverse body bias signal. The bias generator may include a charge pump to output (or provide) a reference voltage to a reference generator, which in turn provides reference signals to the central bias generator. As a result, the local bias generator may control the body bias signal provided by the local bias generator.
摘要:
Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.
摘要:
A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要:
A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.