公开(公告)号：US07314174B1

公开(公告)日：2008-01-01

申请号：US10970964

申请日：2004-10-22

申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

IPC分类号： G06K7/10 ,  G06K9/36 ,  G06K9/80

CPC分类号： H03K19/177

摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.

摘要翻译： 一种用于在集成电路中编程配置存储单元的系统。 该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。

公开(公告)号：US07312631B1

公开(公告)日：2007-12-25

申请号：US11264405

申请日：2005-11-01

申请人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

发明人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/00

CPC分类号： H03K19/17736 ,  H03K19/00323

摘要： Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

摘要翻译： 在PLD中实现的设计中避免持续时间违规的结构和方法。 在可编程设备中，信号路径的延迟例如取决于信号的源和目的地之间的间隔而变化。 在可编程互连结构和具有相对于源的时钟偏移的目的地逻辑元件之间提供可选的延迟元件。 可选延迟元件由实现软件编程，以在必要时在信号路径上引入延迟以满足目的地逻辑元件的保持时间要求。 可选延迟被设计为足够大，以克服即使对于最大可能的时钟偏移和尽可能小的信号延迟的保持时间违规。 当没有发生保持时间违规时，可选的延迟元件被配置为绕过附加延迟，以避免对信号施加大的设置要求。

公开(公告)号：US07279929B1

公开(公告)日：2007-10-09

申请号：US11152439

申请日：2005-06-14

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/17736

摘要： A programmable integrated circuit (IC) includes rows and columns of tiles, each tile including logic blocks, segments of interconnect lines, and programmable structures (e.g., routing multiplexers, input multiplexers). Some interconnect lines can be used to interconnect two programmable structures included in tiles located in different rows and different columns. Thus, these “diagonal” interconnect lines also have programmable access to other programmable interconnect lines (e.g., straight interconnect lines and/or other diagonal interconnect lines) in the general interconnect structure. In some embodiments, the diagonal interconnect lines include “doubles”, which interconnect programmable structures in tiles diagonally adjacent to one another, and “pents”, which interconnect programmable structures in tiles separated by two intervening rows (or columns) and one intervening column (or row). In some embodiments, a diagonal interconnect line coupled between first and second tiles includes an interconnection to a programmable structure in a tile at a “corner” of the diagonal interconnect line.

摘要翻译： 可编程集成电路（IC）包括瓦片的行和列，每个瓦片包括逻辑块，互连线段和可编程结构（例如，路由多路复用器，输入多路复用器）。 一些互连线可用于互连包含在不同行和不同列中的瓷砖中的两个可编程结构。 因此，这些“对角线”互连线还具有对通用互连结构中的其它可编程互连线（例如，直互连线和/或其它对角线互连线）的可编程访问。 在一些实施例中，对角互连线包括“双重”，其将彼此对角地相邻的瓦片中的可编程结构互连，并将“两用”互连在由两个中间行（或列）和一个中间列（ 或行）。 在一些实施例中，耦合在第一和第二瓦片之间的对角互连线包括与对角互连线的“拐角”处的瓦片中的可编程结构的互连。

公开(公告)号：US07276934B1

公开(公告)日：2007-10-02

申请号：US11152637

申请日：2005-06-14

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/17736

摘要： A programmable integrated circuit (IC) includes rows and columns of tiles, each tile including logic blocks, segments of interconnect lines, and programmable structures (e.g., routing multiplexers driving the interconnect lines, input multiplexers driving the logic blocks). The interconnect lines can be used, for example, to interconnect two programmable structures included in tiles located in different rows and different columns. Thus, these “diagonal” interconnect lines also have programmable access to other diagonal interconnect lines in the general interconnect structure. In some embodiments, the diagonal interconnect lines include “doubles”, which interconnect programmable structures in tiles diagonally adjacent to one another, and “pents”, which interconnect programmable structures in tiles separated by two intervening rows (or columns) and one intervening column (or row). In some embodiments, a diagonal interconnect line coupled between first and second tiles include an interconnection to a programmable structure in a tile at the “corner” of the diagonal interconnect line.

摘要翻译： 可编程集成电路（IC）包括瓦片的行和列，每个瓦片包括逻辑块，互连线段和可编程结构（例如，驱动互连线的路由多路复用器，驱动逻辑块的输入多路复用器）。 互连线可以用于例如将包括在位于不同行和不同列中的瓦片中的两个可编程结构互连。 因此，这些“对角线”互连线还可以对通用互连结构中的其它对角线互连线进行可编程访问。 在一些实施例中，对角互连线包括“双重”，其将彼此对角地相邻的瓦片中的可编程结构互连，并将“两用”互连在由两个中间行（或列）和一个中间列（ 或行）。 在一些实施例中，耦合在第一和第二瓦片之间的对角线互连线包括与对角线互连线的“拐角处”的瓦片中的可编程结构的互连。

公开(公告)号：US07274214B1

公开(公告)日：2007-09-25

申请号：US11151938

申请日：2005-06-14

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17796

摘要： In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and at least one column of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. An output terminal of the logic block drives a vertically adjacent subset of the routing multiplexers in the column. Optionally, the tile also includes a second column of routing multiplexers. The logic block output terminal also drives a vertically adjacent subset of the routing multiplexers in the second column, and in some embodiments the two subsets are physically located in horizontal alignment with one another within the tile. The tile can also include a column of input multiplexers for the logic block. The logic block output terminal also drives a vertically adjacent subset of the input multiplexers, and the subsets of routing multiplexers and input multiplexers can be horizontally aligned within the tile.

摘要翻译： 在包括基本相似的瓦片的阵列的集成电路中，瓦片包括逻辑块和驱动可用于可编程地互连逻辑块的互连线的至少一列路由多路复用器。 逻辑块的输出端驱动列中的路由多路复用器的垂直相邻子集。 可选地，瓦片还包括第二列路由多路复用器。 逻辑块输出端还驱动第二列中的路由多路复用器的垂直相邻子集，并且在一些实施例中，两个子集物理地位于瓦片内彼此水平对准。 瓦片还可以包括用于逻辑块的一列输入多路复用器。 逻辑块输出端还驱动输入多路复用器的垂直相邻子集，并且路由多路复用器和输入多路复用器的子集可以在片内水平对准。

公开(公告)号：US07253658B1

公开(公告)日：2007-08-07

申请号：US11152359

申请日：2005-06-14

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： A programmable integrated circuit (IC) provides high routing flexibility without the use of an output multiplexer structure. According to one embodiment, an IC includes programmable tiles arrayed in rows and columns. Output multiplexer structures are not included in the programmable tiles. Routing flexibility is provided in each tile by input multiplexers coupled between a general interconnect structure and the input terminals of a logic block, and by providing direct access from the logic block output terminals (e.g., lookup table outputs and memory element outputs) to both horizontal and vertical interconnect lines. In some embodiments, the logic block output signals can also drive “diagonal” interconnect lines in the general interconnect structure.

摘要翻译： 可编程集成电路（IC）在不使用输出多路复用器结构的情况下提供高路由灵活性。 根据一个实施例，IC包括排列成行和列的可编程瓦片。 输出多路复用器结构不包括在可编程瓦片中。 通过耦合在通用互连结构和逻辑块的输入端之间的输入多路复用器，并且通过提供从逻辑块输出端（例如查找表输出和存储元件输出）到水平方向的直接访问，在每个块中提供路由灵活性 和垂直互连线。 在一些实施例中，逻辑块输出信号还可以驱动通用互连结构中的“对角线”互连线。

公开(公告)号：US07218139B1

公开(公告)日：2007-05-15

申请号：US11151915

申请日：2005-06-14

申请人： Steven P. Young ,  Trevor J. Bauer

发明人： Steven P. Young ,  Trevor J. Bauer

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/1736 ,  G06F1/03 ,  G06F7/57

摘要： Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate both an exclusive OR (XOR) function of first and second input signals and a second function. In some embodiments, the second function is simply the second input signal to the XOR function. In other embodiments, the second function is a different function optionally independent of the first and second input signals. The XOR function output drives the select terminal of a carry multiplexer, which selects between a carry in signal and one of the second input signal and the second function output signal to provide the carry out output signal. The sum or multiplier output value is provided by an XOR gate driven by the XOR function output and by the carry in signal, and can be optionally registered.

摘要翻译： 可编程IC中算术功能的高效实现包括由双输出可编程功能发生器驱动的进位链多路复用器。 具有两个输出信号的函数发生器被编程以产生第一和第二输入信号的异或（XOR）功能和第二功能。 在一些实施例中，第二功能仅仅是到异或功能的第二输入信号。 在其他实施例中，第二功能是可选地独立于第一和第二输入信号的不同功能。 XOR功能输出驱动进位多路复用器的选择端，它在进位信号和第二输入信号之一和第二功能输出信号之间进行选择，以提供进位输出信号。 总和或乘法器输出值由XOR功能输出和进位输入信号驱动的异或门提供，可以任意注册。

公开(公告)号：US07205790B1

公开(公告)日：2007-04-17

申请号：US11152010

申请日：2005-06-14

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： Efficient implementations of wide logic functions (e.g., priority encoders, AND gates, OR gates) in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate first and second function output signals. The first and second functions can optionally share some or all of the input signals. The first function output signal drives the select terminal of a carry multiplexer, which selects between a carry in input signal and the second function output signal to provide the carry out output signal. The wide function result is provided by the final carry multiplexer in a chain of such carry multiplexers. In an exemplary wide AND gate, the first function is an AND function, and the second function is ground. In an exemplary wide OR gate, the first function is a NOR function, and the second function is power high VDD.

摘要翻译： 可编程IC中的宽逻辑功能（例如，优先编码器，与门，或门）的有效实现包括由双输出可编程功能发生器驱动的进位链多路复用器。 具有两个输出信号的函数发生器被编程以产生第一和第二功能输出信号。 第一和第二功能可以可选地共享一些或全部输入信号。 第一功能输出信号驱动进位多路复用器的选择端，其在输入信号的进位和第二功能输出信号之间进行选择以提供进位输出信号。 广泛的功能结果由这种进位多路复用器的链中的最终进位多路复用器提供。 在一个示例性的大AND门中，第一功能是AND功能，第二功能是接地的。 在示例性的“或”门中，第一个功能是NOR功能，第二个功能是高电平VDD。

公开(公告)号：US07193433B1

公开(公告)日：2007-03-20

申请号：US11151988

申请日：2005-06-14

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/177

摘要： A programmable logic block provides to a carry chain multiplexer an output signal representing a partial output signal from a programmable lookup table (LUT), e.g., an output signal having a value that depends upon fewer than all of the data input signals of the LUT. In one embodiment, a first LUT output terminal provides a signal that depends upon fewer than all of the LUT data input signals, and the second LUT output terminal provides a signal that depends upon all of the LUT data input signals. In another embodiment, the first output signal depends upon X of the input signals and the second output signal depends upon Y of the input signals, X and Y being positive integers, X being less than Y. The first LUT output terminal drives a data input terminal, and the second LUT output terminal drives a select input terminal, of the carry chain multiplexer.

摘要翻译： 可编程逻辑块向进位链多路复用器提供表示来自可编程查找表（LUT）的部分输出信号的输出信号，例如具有取决于LUT的数据输入信号少于所有数据的值的输出信号。 在一个实施例中，第一LUT输出端提供取决于少于所有LUT数据输入信号的信号，并且第二LUT输出端提供取决于所有LUT数据输入信号的信号。 在另一个实施例中，第一输出信号取决于输入信号的X，​​第二输出信号取决于输入信号的Y，X和Y是正整数，X小于Y.第一LUT输出端驱动数据输入 终端，第二LUT输出端驱动进位链多路复用器的选择输入端。

公开(公告)号：US07142442B1

公开(公告)日：2006-11-28

申请号：US10796750

申请日：2004-03-08

申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

IPC分类号： G11C5/06 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C7/12 ,  G11C11/41 ,  G11C11/419 ,  G11C2029/1204

摘要： A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.

摘要翻译： 存储器包括多个行段，其中每个行段具有耦合到对应的数据段段对的多个存储器单元。 数据线驱动器电路提供在行段之间以缓冲相邻数据段上的信号。 控制电路耦合到至少一个行段，并且向至少一个行段和数据线驱动器电路提供控制信号。