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    Decision feedback equalizer having programmable taps
    33.
    发明授权
    Decision feedback equalizer having programmable taps 有权
    具有可编程抽头的判决反馈均衡器

    公开(公告)号：US08971395B2

    公开(公告)日：2015-03-03

    申请号：US13293513

    申请日：2011-11-10

    申请人： Ming-Chieh Huang ,  Jing Jing Chen ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei

    发明人： Ming-Chieh Huang ,  Jing Jing Chen ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei

    IPC分类号： H03H7/30 ,  H04L25/03

    CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

    摘要： A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

    摘要翻译： 具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。 延迟元素与夏天相结合。 延迟元件串联连接。 每个延迟元件向延迟元件提供输入信号的相应延迟信号。 重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。 基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号 通过通道传输的脉冲信号。

    Phase locked loop calibration
    34.
    发明授权
    Phase locked loop calibration 有权
    锁相环校准

    公开(公告)号：US08698566B2

    公开(公告)日：2014-04-15

    申请号：US13252498

    申请日：2011-10-04

    申请人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Fu-Lung Hsueh ,  Yuwen Swei

    发明人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Fu-Lung Hsueh ,  Yuwen Swei

    IPC分类号： H03L7/085 ,  H03L7/10 ,  H03B5/12

    CPC分类号： H03L7/102 ,  H03L7/099 ,  H03L2207/06

    摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

    摘要翻译： 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。

    Slicer and method of operating the same
    35.
    发明授权
    Slicer and method of operating the same 有权
    切片机及其操作方法

    公开(公告)号：US08643422B1

    公开(公告)日：2014-02-04

    申请号：US13547396

    申请日：2012-07-12

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Derek C. Tao

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Derek C. Tao

    IPC分类号： H03K3/356

    CPC分类号： H03K5/08 ,  H03K3/356139 ,  H04L27/01

    摘要： This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.

    摘要翻译： 该描述涉及包括第一锁存器的限幅器。 第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。 第一时钟信号与第二时钟信号不同。 第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。 第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。 第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。 切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。 切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

    Current-controlled oscillator (CCO) based PLL
    37.
    发明授权
    Current-controlled oscillator (CCO) based PLL 有权
    基于电流控制振荡器（CCO）的PLL

    公开(公告)号：US08432204B1

    公开(公告)日：2013-04-30

    申请号：US13344637

    申请日：2012-01-06

    申请人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei ,  Fu-Lung Hsueh

    发明人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei ,  Fu-Lung Hsueh

    IPC分类号： H03L7/06

    CPC分类号： H03L7/102 ,  H03L7/099 ,  H03L7/104

    摘要： A PLL circuit includes a phase frequency detector; a programmable charge pump coupled to an output of the phase frequency detector; a loop filter coupled to an output of the charge pump, the loop filter providing a fine tuning voltage; a first voltage-to-current converter, the first voltage-to-current converter providing a fine tuning current corresponding to the fine tuning voltage; a current-controlled oscillator (CCO); a feedback divider coupled to an output of the CCO and an input of the phase frequency detector; and an analog calibration circuit. The analog calibration circuit provides a coarse adjustment current for coarse adjustments to a frequency pivot point for an oscillator frequency of the CCO, wherein the CCO generates a frequency signal at an output responsive to a summed coarse adjustment and fine tuning current, wherein the frequency pivot point is continuously adjustable.

    摘要翻译： PLL电路包括相位检波器; 耦合到所述相位频率检测器的输出的可编程电荷泵; 耦合到电荷泵的输出的环路滤波器，所述环路滤波器提供微调电压; 第一电压 - 电流转换器，第一电压 - 电流转换器提供对应于微调电压的微调电流; 电流控制振荡器（CCO）; 耦合到CCO的输出的反馈分压器和相位频率检测器的输入端; 和模拟校准电路。 模拟校准电路提供用于对CCO的振荡器频率的频率枢转点进行粗调整的粗调电流，其中CCO响应于总和的粗调和微调电流而在输出端产生频率信号，其中频率枢轴 点连续可调。

    Voltage regulator with high accuracy and high power supply rejection ratio
    38.
    发明授权
    Voltage regulator with high accuracy and high power supply rejection ratio 有权
    电压调节器具有高精度和高电源抑制比

    公开(公告)号：US08378654B2

    公开(公告)日：2013-02-19

    申请号：US12750260

    申请日：2010-03-30

    申请人： Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

    发明人： Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

    IPC分类号： G05F1/44

    CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

    摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

    摘要翻译： 提供了具有高精度和电源抑制比（PSRR）的稳压电路。 在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。 在另一个实施例中，PMOS和NMOS晶体管的作用相反。

    Regulators regulating charge pump and memory circuits thereof
    39.
    发明授权
    Regulators regulating charge pump and memory circuits thereof 有权
    调节电荷泵及其存储电路的调节器

    公开(公告)号：US08223576B2

    公开(公告)日：2012-07-17

    申请号：US12716430

    申请日：2010-03-03

    申请人： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    发明人： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    IPC分类号： G11C5/14

    CPC分类号： G11C5/145 ,  G11C11/4074

    摘要： A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.

    摘要翻译： 提供了一种用于调节电荷泵的调节器。 调节器包括具有能够接收第一电压的第一输入端和能够接收用于确定启动或禁用电荷泵的第二电压的第二输入端的比较器。 第一电压与电荷泵的输出电压相关联。 第二电压与内部电源电压和参考电压Vref相关联。

    Regulators regulating charge pump and memory circuits thereof
    40.
    发明授权
    Regulators regulating charge pump and memory circuits thereof 有权
    调节电荷泵及其存储电路的调节器

    公开(公告)号：US08456942B2

    公开(公告)日：2013-06-04

    申请号：US13535034

    申请日：2012-06-27

    申请人： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    发明人： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    IPC分类号： G11C5/14

    CPC分类号： G11C5/145 ,  G11C11/4074

    摘要： A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.

    摘要翻译： 提供了一种用于调节电荷泵的调节器。 调节器包括具有能够接收第一电压的第一输入端和能够接收用于确定启动或禁用电荷泵的第二电压的第二输入端的比较器。 第一电压与电荷泵的输出电压相关联。 第二电压与内部电源电压和参考电压Vref相关联。