公开(公告)号：US08458383B1

公开(公告)日：2013-06-04

申请号：US11848016

申请日：2007-08-30

申请人： Curt Wortman ,  Chong H. Lee ,  Divya Vijayaraghavan ,  Ning Xue

发明人： Curt Wortman ,  Chong H. Lee ,  Divya Vijayaraghavan ,  Ning Xue

IPC分类号： G06F13/14 ,  G06F15/16

CPC分类号： G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

摘要： On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.

摘要翻译： 在可编程设备上，用于具有包括至少物理层，数据链路层和事务层的协议栈的协议的可编程接口的每层可选择地旁路。 当旁路一层时，该层下游的所有其他层也被旁路。 此外，该接口可以被划分为以不同的时钟速率运行的不同的时钟域，反映了可编程器件内部和可编程器件外部的时钟速率。 可以绕过图层以允许用户替换可编程逻辑中的自定义层，或者替换更新的层进行调试。

公开(公告)号：US08165191B2

公开(公告)日：2012-04-24

申请号：US12288178

申请日：2008-10-17

申请人： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： H04B1/005 ,  G06F13/385 ,  H04L69/12 ,  H04L69/18

摘要： Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.

摘要翻译： 本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。 可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。 所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路 从属（“PMD”）子层电路。

公开(公告)号：US08098087B1

公开(公告)日：2012-01-17

申请号：US11682282

申请日：2007-03-05

申请人： John Dung-Ngoc Lam ,  Arch Zaliznyak ,  Wilson Wong ,  Tin H. Lai ,  Chong H. Lee ,  Sergey Shumarayev

发明人： John Dung-Ngoc Lam ,  Arch Zaliznyak ,  Wilson Wong ,  Tin H. Lai ,  Chong H. Lee ,  Sergey Shumarayev

IPC分类号： H03K5/08

CPC分类号： H04L25/03878 ,  H03K5/249

摘要： A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.

摘要翻译： 提供了一种方法和装置，用于在接收器通道内的比较器的输入处的待机电压偏移消除。 第一比较器输入和第二比较器输入中的每一个与输入信号隔离，使得第一和第二比较器输入中的每一个达到相应的待机电压电平。 在第一和第二比较器输入之一上的电压电平递增地改变，同时监视比较器的输出信号。 在检测到比较器的输出信号中的状态转变时，一个比较器输入端的电压电平的增量变化在最终电压电平设置下停止。 最后的电压电平设置存储在计算机存储器中，用于参考在一个比较器输入处的电压电平的设置，以便补偿在比较器的输入处的待机电压偏移。

公开(公告)号：US07925913B1

公开(公告)日：2011-04-12

申请号：US11857141

申请日：2007-09-18

申请人： Divya Vijayaraghavan ,  Michael Menghui Zheng ,  Lana May Chan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Michael Menghui Zheng ,  Lana May Chan ,  Chong H. Lee

IPC分类号： G06F1/00 ,  H04L7/00 ,  H04L7/02

CPC分类号： G06F13/4295 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/10 ,  Y02D10/14 ,  Y02D10/151

摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.

摘要翻译： 可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电空闲周期之间切换其“锁定参考”（“LTR”）状态和 其正常的“锁定数据”（“LTD”）状态。 无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号 已经接收到数据并发生字节同步。 预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。 优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。 从而避免了不可靠的模拟信号检测。

公开(公告)号：US07869343B1

公开(公告)日：2011-01-11

申请号：US11447745

申请日：2006-06-05

申请人： Ning Xue ,  Chong H. Lee

发明人： Ning Xue ,  Chong H. Lee

IPC分类号： G06F11/00

CPC分类号： H04L1/0041

摘要： A field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) includes relatively general-purpose PLD core circuitry and relatively specialized high-speed serial interface (“HSSI”) hard IP circuitry. To better support applications that include forward error correction (“FEC”), some tasks related to FEC (e.g., FIFO operations) are performed in the PLD core circuitry, while other FEC tasks (e.g., FEC calculations) are performed in the HSSI hard IP circuitry.

摘要翻译： 现场可编程门阵列（“FPGA”）或可编程逻辑器件（“PLD”）包括相对通用的PLD核心电路和相对专门的高速串行接口（“HSSI”）硬IP电路。 为了更好地支持包括前向纠错（“FEC”）的应用，在PLD核心电路中执行与FEC相关的一些任务（例如FIFO操作），而在HSSI硬执行其他FEC任务（例如，FEC计算） IP电路。

公开(公告)号：US06888376B1

公开(公告)日：2005-05-03

申请号：US10670845

申请日：2003-09-24

申请人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/1778 ,  H03K19/17796

摘要： A serial interface for a programmable logic device supports a higher physical medium attachment (“PMA”) data rate than the available physical coding sublayer (“PCS”) data rate by using multiple PCS modules, operating in parallel, to support one PMA module. In a channel-based structure, the PMA module is supported by a PCS module in its own channel and at least one PCS module from a second channel. The second channel may include its own PMA module which, if provided, may operate at a lower rate, supportable by the PCS module in that channel. Optionally, two modes are provided. In one mode, two PCS modules in two channels support one higher-speed PMA module in one of the channels. In a second mode, each PCS module supports a PMA module in its own channel, with the higher-speed PMA module constrained to operate at the lower data rate of the PCS module.

摘要翻译： 用于可编程逻辑器件的串行接口通过使用并行操作的多个PCS模块来支持比可用物理编码子层（“PCS”）数据速率更高的物理介质附加（“PMA”）数据速率，以支持一个PMA模块。 在基于通道的结构中，PMA模块由其自身通道中的PCS模块和来自第二通道的至少一个PCS模块支持。 第二通道可以包括其自己的PMA模块，如果提供的话，该模块可以以较低的速率操作，由PCS模块在该通道中支持。 可选地，提供两种模式。 在一种模式下，两个通道中的两个PCS模块在其中一个通道中支持一个更高速的PMA模块。 在第二种模式下，每个PCS模块都支持自己的通道中的PMA模块，而高速PMA模块则被限制在PCS模块的较低数据速率下工作。

公开(公告)号：US06650140B2

公开(公告)日：2003-11-18

申请号：US10093785

申请日：2002-03-06

申请人： Chong H. Lee ,  Reza Asayesh

发明人： Chong H. Lee ,  Reza Asayesh

IPC分类号： H03K19177

CPC分类号： H03K19/17744 ,  H03K19/17732

摘要： A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

公开(公告)号：US08788862B1

公开(公告)日：2014-07-22

申请号：US13175745

申请日：2011-07-01

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： G06F1/32

CPC分类号： G06F1/3278 ,  Y02D10/157 ,  Y02D50/20

摘要： A method and system for efficiently transitioning a communication circuit from a low-power state are disclosed. A first device and second device in a low-power state may be transitioned to an active state to enable the transmission of data over a communication link, where energy consumption of one or more components of the first and/or second devices may be reduced in the low-power state. The transition may be initiated by the first device responsive to a signal and/or an expiration of a timer. Responsive thereto, a scrambler of the first device may be temporarily bypassed to accelerate achieving block lock at the second device, thereby enabling the system to more quickly transition from the low-power state to the active state.

摘要翻译： 公开了一种将通信电路从低功率状态有效地转变的方法和系统。 处于低功率状态的第一设备和第二设备可以被转换到活动状态，以便能够通过通信链路传输数据，其中可以减少第一和/或第二设备中的一个或多个组件的能量消耗 低功耗状态。 第一设备可以响应于信号和/或定时器的期满而启动转换。 响应于此，第一设备的加扰器可能被暂时旁路以加速实现第二设备处的块锁定，从而使得系统能够更快地从低功率状态转换到活动状态。

公开(公告)号：US08732375B1

公开(公告)日：2014-05-20

申请号：US12752641

申请日：2010-04-01

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： G06F13/14

CPC分类号： G06F13/385

摘要： Structures and methods are disclosed relating to a multi-protocol transceiver including lane-based Physical Coding Sublayer (“PCS”) circuitry that is configurable to adapt to one of a plurality of communication protocols. Particular embodiments of the present invention include lane based configurable data paths through PCS transmit and receive circuitry.

摘要翻译： 公开了涉及包括基于通道的物理编码子层（“PCS”）电路的多协议收发器的结构和方法，该电路可配置为适应多个通信协议之一。 本发明的特定实施例包括通过PCS发送和接收电路的基于通道的可配置数据路径。

公开(公告)号：US20120307878A1

公开(公告)日：2012-12-06

申请号：US12860482

申请日：2010-08-20

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04B3/46 ,  H04L27/00

CPC分类号： H04L5/1446 ,  H04L1/0002 ,  H04L1/0025

摘要： An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.

摘要翻译： 用于本地设备的接口包括可编程地配置为至少三个数据速率的发射机部分，可编程地配置为至少三个数据速率的接收机部分，以及可操作地连接到发射机部分和接收机部分的自动速度协商模块 配置发射机部分和接收机部分，以与作为这些至少三个数据速率中最好的可用数据速率的单个数据速率与远程设备进行通信。 可以通过调整发射机数据路径宽度和接收机数据路径宽度，调整所述发射机数据路径和所述接收机数据路径的频率以及过采样来调整日期速率。 可以使能或禁用字节序列化或反序列化，以根据数据速率改变数据的宽度，以传输到/从本地设备的其余部分。