公开(公告)号：US12183834B2

公开(公告)日：2024-12-31

申请号：US18046433

申请日：2022-10-13

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Sayeef Salahuddin ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H10B43/30

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

公开(公告)号：US12052867B2

公开(公告)日：2024-07-30

申请号：US17348603

申请日：2021-06-15

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/768 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76837 ,  H01L21/76843 ,  H01L29/40117 ,  H10B43/35

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US20240040798A1

公开(公告)日：2024-02-01

申请号：US18483322

申请日：2023-10-09

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Christopher J. Petti ,  Vinod Purayath ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

CPC classification number: H10B51/30 ,  G11C11/2275 ,  G11C11/2273 ,  G11C11/223 ,  H10B51/20

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

公开(公告)号：US20230065451A1

公开(公告)日：2023-03-02

申请号：US18046433

申请日：2022-10-13

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Sayeef Salahuddin ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/423

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

公开(公告)号：US20220173251A1

公开(公告)日：2022-06-02

申请号：US17674137

申请日：2022-02-17

Applicant: SUNRISE MEMORY CORPORATION

Inventor： George Samachisa ,  Vinod Purayath ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/66 ,  H01L29/786

Abstract: By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors (“FeFETs”), thereby providing a very high-speed, high-density memory array.

公开(公告)号：US20220165751A1

公开(公告)日：2022-05-26

申请号：US17669024

申请日：2022-02-10

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Wu-Yi Henry Chien ,  Jie Zhou ,  Eli Harari

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L21/311

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

公开(公告)号：US11217600B2

公开(公告)日：2022-01-04

申请号：US16924531

申请日：2020-07-09

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Wu-Yi Henry Chien

IPC: H01L27/105 ,  H01L27/11578 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/768 ,  H01L29/66 ,  H01L21/28

Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.

公开(公告)号：US11069711B2

公开(公告)日：2021-07-20

申请号：US16894624

申请日：2020-06-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/28 ,  H01L27/1157

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US11049873B2

公开(公告)日：2021-06-29

申请号：US16578970

申请日：2019-09-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Chenming Hu ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/02 ,  H01L21/28

Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.

公开(公告)号：US10818692B2

公开(公告)日：2020-10-27

申请号：US16792790

申请日：2020-02-17

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Scott Brad Herner ,  Wu-Yi Henry Chien

IPC: H01L21/00 ,  H01L27/11582 ,  H01L27/11578 ,  H01L23/00 ,  H01L21/768 ,  H01L21/311 ,  G11C16/04

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.