公开(公告)号：US20080283963A1

公开(公告)日：2008-11-20

申请号：US11748959

申请日：2007-05-15

申请人： Shine Chung ,  Fu-Lung Hsueh ,  Fu-Chieh Hsu

发明人： Shine Chung ,  Fu-Lung Hsueh ,  Fu-Chieh Hsu

IPC分类号： H01L23/62 ,  H01L29/00

CPC分类号： G11C17/18

摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

摘要翻译： 公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接， 以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流 保险丝编程操作。

公开(公告)号：US20060114140A1

公开(公告)日：2006-06-01

申请号：US10998389

申请日：2004-11-29

申请人： Fu-Lung Hsueh

发明人： Fu-Lung Hsueh

IPC分类号： H03M1/12

CPC分类号： H03M1/146

摘要： This invention discloses a method for converting an analog signal to a digital signal as the following steps. A reference voltage range is divided into a plurality of reference levels. The analog signal is compared with the reference levels to generate first conversion bits. A reference voltage sub-range defined by a first value and a second value of the reference level is selected, wherein the voltage level of the analog signal is higher than the first value and lower than the second value. The reference voltage sub-range is divided into a plurality of reference sub-levels. The analog signal is compared with the reference sub-levels to generate second conversion bits. The digital signal representing the analog signal is generated based on the first-conversion bits and the second conversion bits.

摘要翻译： 本发明公开了一种将模拟信号转换为数字信号的方法，如下步骤。 参考电压范围被分成多个参考电平。 将模拟信号与参考电平进行比较以产生第一转换位。 选择由参考电平的第一值和第二值定义的参考电压子范围，其中模拟信号的电压电平高于第一值并低于第二值。 参考电压子范围被分成多个参考子电平。 将模拟信号与参考子电平进行比较以产生第二转换位。 代表模拟信号的数字信号是基于第一转换位和第二转换位产生的。

公开(公告)号：US06608580B2

公开(公告)日：2003-08-19

申请号：US09784792

申请日：2001-02-15

申请人： Fu-Lung Hsueh

发明人： Fu-Lung Hsueh

IPC分类号： H03M112

CPC分类号： H03M1/0682 ,  H03M1/46

摘要： A method and system for converting a plurality of input signals being indicative of a signal to be converted to a digital output including: setting a plurality of codes each being indicative of a corresponding reference level; and, for each one of the codes, converting the one code to a first analog signal, and summing the first analog signal with a first of the input signals to provide a first summed signal; complementing the one code to provide a complemented code, converting the complemented code to a second analog signal; summing the second analog signal with a second of the input signals to provide a second summed signal corresponding to the first summed signal. The corresponding first and second summed signals are compared to provide a comparison signal. At least a portion of the digital output is set according to the comparison signal.

公开(公告)号：US06229506B1

公开(公告)日：2001-05-08

申请号：US09064696

申请日：1998-04-22

申请人： Robin Mark Adrian Dawson ,  Michael Gillis Kane ,  James Ya-Kong Hsu ,  Fu-Lung Hsueh ,  Alfred Charles Ipri ,  Roger Green Stewart

发明人： Robin Mark Adrian Dawson ,  Michael Gillis Kane ,  James Ya-Kong Hsu ,  Fu-Lung Hsueh ,  Alfred Charles Ipri ,  Roger Green Stewart

IPC分类号： G09G332

CPC分类号： G09G3/3233 ,  G09G3/325 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/02 ,  G09G2320/043

摘要： A LED pixel structure that reduces current nonuniformities and threshold voltage variations in a “drive transistor”of the pixel structure is disclosed. The LED pixel structure incorporates a current source for loading data into the pixel via a data line. Alternatively, an auto zero voltage is determined for the drive transistor prior to the loading of data.

摘要翻译： 公开了一种降低像素结构的“驱动晶体管”中的电流不均匀性和阈值电压变化的LED像素结构。 LED像素结构包含用于经由数据线将数据加载到像素中的电流源。 或者，在加载数据之前，确定驱动晶体管的自动零电压。

公开(公告)号：US06104041A

公开(公告)日：2000-08-15

申请号：US87570

申请日：1998-05-29

申请人： Fu-Lung Hsueh ,  Alfred Charles Ipri

发明人： Fu-Lung Hsueh ,  Alfred Charles Ipri

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  H01L29/404 ,  H01L29/78624

摘要： In an active matrix electroluminescent display, a pixel containing a electroluminescent cell and the switching electronics for the electroluminescent cell where said switching electronics contains two transistors, a low voltage MOS transistor and a high voltage MOS transistor. A low voltage transistor is controlled by signals on a data and a select line. When activated, the low voltage transistor activates the high voltage transistor by charging the gate of the high voltage transistor. The gate charge is stored between the gate electrode of the high voltage transistor and an electric field shield forming a pixel signal capacitor. The pixel signal capacitor is positioned within the layout of the pixel a distance from the drain of the high voltage MOS transistor.

摘要翻译： 在有源矩阵电致发光显示器中，包含电致发光单元的像素和用于电致发光单元的开关电子器件，其中所述开关电子器件包含两个晶体管，低电压MOS晶体管和高压MOS晶体管。 低电压晶体管由数据和选择线上的信号控制。 当激活时，低压晶体管通过对高电压晶体管的栅极充电来激活高电压晶体管。 栅极电荷存储在高压晶体管的栅电极和形成像素信号电容器的电场屏蔽之间。 像素信号电容器位于与高压MOS晶体管的漏极相距一定距离的像素的布局内。

公开(公告)号：US5291198A

公开(公告)日：1994-03-01

申请号：US887761

申请日：1992-05-29

申请人： Andrew G. F. Dingwall ,  Fu-Lung Hsueh

发明人： Andrew G. F. Dingwall ,  Fu-Lung Hsueh

IPC分类号： H03M1/20 ,  H03M1/36

CPC分类号： H03M1/204 ,  H03M1/205 ,  H03M1/365

摘要： A flash-type analog-to-digital converter (ADC) uses only 2.sup.n-m comparators coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2.sup.m pseudocomparators which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair of actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks. In other embodiments of the invention the ADC is implemented in CMOS technology and the pseudocomparators use ratioed transistor widths and ratioed capacitors to proportionally divide the output signals of the actual comparators in order to generate the interstitial output values. A final embodiment of the invention combines two averaging flash ADCs to form a novel subranging ADC.

摘要翻译： 闪存型模数转换器（ADC）仅使用耦合到模拟输入线的2n-m个比较器来产生n位数字输出信号。 这些实际比较器中的每一对并联耦合到2m伪同步器，其提供表示将输入信号值与实际比较器使用的参考值之间的相应参考值进行比较的值。 每对实际比较器的输出信号在每个伪同步器上以不同的比例组合。 以这种方式，实际比较器的输出信号被平均以产生间隙比较值。 在本发明的一个实施例中，ADC采用BiCMOS技术实现，具有双极性差分输入级和CMOS锁存比较器。 信号通过一对电阻梯形网络从实际的比较器分布到伪同步器。 在本发明的其他实施例中，ADC以CMOS技术实现，并且伪同步器使用比例的晶体管宽度和比例的电容器来成比例地划分实际比较器的输出信号，以便产生间隙输出值。 本发明的最终实施例组合了两个平均闪光ADC，以形成新型的Subranging ADC。

公开(公告)号：US09397729B2

公开(公告)日：2016-07-19

申请号：US12946072

申请日：2010-11-15

申请人： Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H04B5/00

CPC分类号： H04B5/0081

摘要： Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.

摘要翻译： 芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。 第一线圈耦合到天线。 第二线圈耦合到放大器电路。 第二线圈不与第一线圈直接接触。 第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。

公开(公告)号：US09165968B2

公开(公告)日：2015-10-20

申请号：US13616850

申请日：2012-09-14

申请人： Calvin Yi-Ping Chao ,  Kuo-Yu Chou ,  Fu-Lung Hsueh

发明人： Calvin Yi-Ping Chao ,  Kuo-Yu Chou ,  Fu-Lung Hsueh

IPC分类号： H01L27/146 ,  H04N5/374

CPC分类号： H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H04N5/374

摘要： A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.

摘要翻译： 提供一种堆叠式图像传感器及其制造方法。 堆叠图像传感器包括其上具有像素阵列的上部芯片。 第二芯片包括与像素阵列的列和行相关联的多个列电路和行电路，并且被布置在多个组中的各个列电路和行电路区域中。 在每个芯片上形成芯片间接合焊盘。 在一个实施例中，第二芯片上的芯片间接合焊盘被线性布置并且被包含在列电路区域和行电路区域内。 在其他实施例中，芯片间接合焊盘相对于彼此交错。 在一些实施例中，像素阵列的行和列包括多个信号线，并且相应的列电路区域和行电路区域还包括多个芯片间接合焊盘。

公开(公告)号：US08890626B2

公开(公告)日：2014-11-18

申请号：US13586033

申请日：2012-08-15

申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Iuan Liu

发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Iuan Liu

IPC分类号： H03K3/03

CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。

公开(公告)号：US08847321B2

公开(公告)日：2014-09-30

申请号：US12766972

申请日：2010-04-26

申请人： Fu-Lung Hsueh ,  Chih-Ping Chao ,  Chewn-Pu Jou ,  Yung-Chow Peng ,  Harry-Hak-Lay Chuang ,  Kuo-Tung Sung

发明人： Fu-Lung Hsueh ,  Chih-Ping Chao ,  Chewn-Pu Jou ,  Yung-Chow Peng ,  Harry-Hak-Lay Chuang ,  Kuo-Tung Sung

IPC分类号： H01L29/78 ,  G06F17/50 ,  H01L27/088

CPC分类号： G06F17/5068 ,  G06F17/50 ,  G06F17/5009 ,  H01L27/088 ,  H01L27/0922

摘要： A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

摘要翻译： MOS器件包括具有第一和第二触点的有源区。 第一和第二栅极设置在第一和第二触点之间。 第一门被设置成与第一接触相邻并且具有第三接触。 第二栅极被设置成与第二触点相邻并且具有耦合到第三触点的第四触点。 由有源区和第一栅极限定的晶体管具有第一阈值电压，并且由有源区和第二栅极限定的晶体管具有第二阈值电压。