公开(公告)号：US08890626B2

公开(公告)日：2014-11-18

申请号：US13586033

申请日：2012-08-15

申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Iuan Liu

发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Iuan Liu

IPC分类号： H03K3/03

CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。

公开(公告)号：US08476972B2

公开(公告)日：2013-07-02

申请号：US12813620

申请日：2010-06-11

申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： G06G7/12 ,  G06G7/26

CPC分类号： G04F10/005

摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

公开(公告)号：US08193963B2

公开(公告)日：2012-06-05

申请号：US12874462

申请日：2010-09-02

申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng-Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng-Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03M1/50

CPC分类号： G04F10/005

摘要： Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

摘要翻译： 公开了时间到数字转换（TDC）的方法和装置。 定时电路包括TDC电路，校准模块和校正模块。 TDC电路被配置为提供指示周期性参考时钟信号的边沿与可变反馈信号之间的定时差的定时信号。 TDC电路还被配置为提供相对于参考时钟信号可变地延迟的延迟信号。 校准模块被配置为提供校准信号，以根据校准信号的时间延迟加上校正信号的时间延迟来增加和减少TDC电路的总延迟。 被配置为接收定时信号并提供校正信号的校正模块通过在参考时钟信号的频率下工作来最小化定时信号的频率响应中的谐波杂散。

公开(公告)号：US08629737B2

公开(公告)日：2014-01-14

申请号：US13544444

申请日：2012-07-09

申请人： Kun-Yin Wang ,  Tao-Yao Chang ,  Chorng-Kuang Wang ,  Shen-Iuan Liu

发明人： Kun-Yin Wang ,  Tao-Yao Chang ,  Chorng-Kuang Wang ,  Shen-Iuan Liu

IPC分类号： H01P5/12 ,  H01F30/06

CPC分类号： G06G7/04 ,  H03F3/602

摘要： The signal processing apparatus contains a first signal transforming circuit and a second signal transforming circuit. The first signal transforming circuit includes four first coupled lines and two second coupled lines, wherein two ends of each first coupled line are configured to carry a first pair of differential signals respectively, each second coupled line is magnetically coupled to two of the first coupled lines in parallel and comprises two signal ports, to which the two ends of each of the magnetically-coupled first coupled lines are placed symmetrically for transferring a second pair of differential signals. The second signal transforming circuit is configured to convert between the second pairs of differential signals at the signal ports and a third pair of differential signals at connecting ports of the second signal transforming circuit.

摘要翻译： 信号处理装置包含第一信号变换电路和第二信号变换电路。 第一信号变换电路包括四个第一耦合线和两个第二耦合线，其中每个第一耦合线的两端被配置为分别承载第一对差分信号，每个第二耦合线被磁耦合到两个第一耦合线 并联并且包括两个信号端口，每个磁耦合的第一耦合线的两端对称地放置在其上以传送第二对差分信号。 第二信号变换电路被配置为在信号端口处的第二对差分信号和第二信号变换电路的连接端口处的第三对差分信号之间进行转换。

公开(公告)号：US07983361B2

公开(公告)日：2011-07-19

申请号：US11957561

申请日：2007-12-17

申请人： Shen-Iuan Liu ,  Chih-Hung Lee ,  Lan-Chou Cho

发明人： Shen-Iuan Liu ,  Chih-Hung Lee ,  Lan-Chou Cho

IPC分类号： H04L27/00

CPC分类号： H04L7/033 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0084 ,  H03L7/0805 ,  H03L7/18 ,  H04L7/0338

摘要： A clock data recovery circuit. The clock data recovery circuit comprises a transmission line, a phase locked loop, a voltage controlled oscillator, a phase selector, and a D flip-flop. The transmission line receives an input signal. The phase locked loop receives the input signal via the transmission line and a reference clock and generates a first clock signal. The voltage controlled oscillator receives the input signal via the transmission line and a control voltage from an internal node of the phase locked loop, and generates a clock signal. The phase selector receives the input signal via the transmission line and the clock signal from the voltage controlled oscillator, and generates a clock output signal. The D flip-flop receives the input signal via the transmission line and the clock output signal, and generates a data output signal.

摘要翻译： 时钟数据恢复电路。 时钟数据恢复电路包括传输线，锁相环，压控振荡器，相位选择器和D触发器。 传输线接收输入信号。 锁相环通过传输线和参考时钟接收输入信号并产生第一时钟信号。 压控振荡器通过传输线接收输入信号，并从锁相环的内部节点接收控制电压，并产生时钟信号。 相位选择器通过传输线接收输入信号和来自压控振荡器的时钟信号，并产生时钟输出信号。 D触发器经由传输线和时钟输出信号接收输入信号，并产生数据输出信号。

公开(公告)号：US07940847B2

公开(公告)日：2011-05-10

申请号：US11645724

申请日：2006-12-27

申请人： Che-Fu Liang ,  Shen-Iuan Liu ,  Gin-Kou Ma ,  Tzu-Yi Yang

发明人： Che-Fu Liang ,  Shen-Iuan Liu ,  Gin-Kou Ma ,  Tzu-Yi Yang

IPC分类号： H04K1/10 ,  H04L27/28

CPC分类号： H04L27/2602 ,  H03L7/0995 ,  H03L7/23

摘要： A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.

摘要翻译： 公开了一种用于产生MB-OFDM UWB系统的多个频率的频率合成器，其中，频率包括从低到高的第一到第十四个频率，并且相邻两个频率中的任一个频率与基本的金属间频率不同。 频率合成器包括产生具有等于第二频率的频率的初始信号的锁相环，产生从低到高的第一到第三个金属间频率的全球频率发生器，并且都是基本的金属间频率的整数，并产生第四个金属间频率 等于基本的金属间频率，以及串联连接的第一至第三混频器，分别接收第四至第三电荷频率，第一至第三电压之间的第一和第四电容间的频率，分别产生第一至第三频率，第四至第九频率 和第十三至第十四频率，以及第十至第十二频率。

公开(公告)号：US5506538A

公开(公告)日：1996-04-09

申请号：US433837

申请日：1995-05-04

申请人： Shen-Iuan Liu

发明人： Shen-Iuan Liu

IPC分类号： G06G7/20 ,  G06G7/22 ,  G06G7/16

CPC分类号： G06G7/22 ,  G06G7/20

摘要： A vector summation device includes a squaring circuit for receiving a number of input voltage signals, and a square-root circuit having first and second current terminals connected electrically to the squaring unit. The squaring circuit receives first and second current signals respectively from the first and second current terminals of the square-root circuit. The difference between the current values of the first and second current signals is proportional to the sum of the squares of the voltage values of the input voltage signals. The square-root circuit generates an output voltage signal with a voltage value that is proportional to the square-root of the difference between the current values of the first and second current signals.

摘要翻译： 矢量求和装置包括用于接收多个输入电压信号的平方电路，以及具有与平方单元电连接的第一和第二电流端子的平方根电路。 平方电路分别从平方根电路的第一和第二电流端接收第一和第二电流信号。 第一和第二电流信号的电流值的差异与输入电压信号的电压值的平方和成正比。 平方根电路产生具有与第一和第二电流信号的电流值之间的差的平方根成比例的电压值的输出电压信号。

公开(公告)号：US08593207B2

公开(公告)日：2013-11-26

申请号：US12613752

申请日：2009-11-06

申请人： Shen-Iuan Liu ,  Chih-Hung Lee

发明人： Shen-Iuan Liu ,  Chih-Hung Lee

IPC分类号： G06G7/12

CPC分类号： H03F3/08 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/258 ,  H03F2203/45638

摘要： A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.

公开(公告)号：US08319525B2

公开(公告)日：2012-11-27

申请号：US12939150

申请日：2010-11-03

申请人： Yun-Ta Tsai ,  Shen-Iuan Liu

发明人： Yun-Ta Tsai ,  Shen-Iuan Liu

IPC分类号： H03D1/00

CPC分类号： H03K19/0963 ,  H03K19/00384

摘要： A flip-flop circuit includes a D flip-flop and a leakage current suppression circuit. The D flip-flop receives an input signal and a clock signal, and outputs a voltage of the input signal at a rising or falling edge of the clock signal as an output signal. The leakage current suppression circuit detects an output error caused by the leakage current flowing through at least a floating node of the D flip-flop and compensates for the leakage current to correct the output error. The leakage current suppression circuit includes a detection circuit and a compensation circuit. The detection circuit receives the output signal and clock signal and detects whether the output error has occurred to generate a detection result. The compensation circuit compensates for the leakage current according to the detection result to correct the output error.

摘要翻译： 触发器电路包括D触发器和漏电流抑制电路。 D触发器接收输入信号和时钟信号，并且在时钟信号的上升沿或下降沿输出输入信号的电压作为输出信号。 泄漏电流抑制电路检测由D触发器的至少浮动节点流过的漏电流引起的输出误差，并补偿漏电流以校正输出误差。 泄漏电流抑制电路包括检测电路和补偿电路。 检测电路接收输出信号和时钟信号，并检测是否发生输出错误以产生检测结果。 补偿电路根据检测结果补偿漏电流，以校正输出误差。

公开(公告)号：US20110241745A1

公开(公告)日：2011-10-06

申请号：US12939150

申请日：2010-11-03

申请人： Yun-Ta TSAI ,  Shen-Iuan Liu

发明人： Yun-Ta TSAI ,  Shen-Iuan Liu

IPC分类号： H03K3/00

CPC分类号： H03K19/0963 ,  H03K19/00384

摘要： A flip-flop circuit includes a D flip-flop and a leakage current suppression circuit. The D flip-flop receives an input signal and a clock signal, and outputs a voltage of the input signal at a rising or falling edge of the clock signal as an output signal. The leakage current suppression circuit detects an output error caused by the leakage current flowing through at least a floating node of the D flip-flop and compensates for the leakage current to correct the output error. The leakage current suppression circuit includes a detection circuit and a compensation circuit. The detection circuit receives the output signal and clock signal and detects whether the output error has occurred to generate a detection result. The compensation circuit compensates for the leakage current according to the detection result to correct the output error.

摘要翻译： 触发器电路包括D触发器和漏电流抑制电路。 D触发器接收输入信号和时钟信号，并且在时钟信号的上升沿或下降沿输出输入信号的电压作为输出信号。 泄漏电流抑制电路检测由D触发器的至少浮动节点流过的漏电流引起的输出误差，并补偿漏电流以校正输出误差。 泄漏电流抑制电路包括检测电路和补偿电路。 检测电路接收输出信号和时钟信号，并检测是否发生输出错误以产生检测结果。 补偿电路根据检测结果补偿漏电流，校正输出误差。