公开(公告)号：US20230197784A1

公开(公告)日：2023-06-22

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/2003 ,  H01L29/0653

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US11508830B2

公开(公告)日：2022-11-22

申请号：US17110811

申请日：2020-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nicholas Stephen Dellas ,  Dong Seup Lee ,  Andinet Tefera Desalegn

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/207 ,  H01L29/06 ,  H01L29/20

Abstract: In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

公开(公告)号：US20220130988A1

公开(公告)日：2022-04-28

申请号：US17081301

申请日：2020-10-27

Applicant: Texas Instruments Incorporated

Inventor： Qhalid RS Fareed ,  Dong Seup Lee ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Fabrication methods, electronic devices and enhancement mode gallium nitride transistors include a gallium nitride interlayer between a hetero-epitaxy structure and a p-doped gallium nitride layer and/or between the p-doped gallium nitride layer and a gate structure to mitigate p-type dopant diffusion, improve current collapse performance, and mitigate positive-bias temperature instability. In certain examples, the interlayer or interlayers is/are fabricated using epitaxial deposition with no p-type dopant source. In certain fabrication process examples, epitaxial deposition or growth is interrupted after the depositing an aluminum gallium nitride layer of the hetero-epitaxy structure, after which growth is resumed to deposit the first gallium nitride interlayer over the aluminum gallium nitride layer to mitigate p-type dopant diffusion and current collapse.

公开(公告)号：US10381456B2

公开(公告)日：2019-08-13

申请号：US15587021

申请日：2017-05-04

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Dong Seup Lee ,  Jungwoo Joh ,  Naveen Tipirneni ,  Sameer Prakash Pendharkar

IPC: H01L29/778 ,  H01L29/66 ,  H01L23/535 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L29/20 ,  H01L27/07 ,  H01L27/088

Abstract: An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.

公开(公告)号：US10312095B1

公开(公告)日：2019-06-04

申请号：US16163602

申请日：2018-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Yoshikazu Kondo ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/205 ,  H01L21/28 ,  H01L29/423 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20

Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

公开(公告)号：US09741557B1

公开(公告)日：2017-08-22

申请号：US15191500

申请日：2016-06-23

Applicant: Texas Instruments Incorporated

Inventor： Nicholas Stephen Dellas ,  Naveen Tipirneni ,  Dong Seup Lee

IPC: H01L29/02 ,  H01L21/02 ,  H01L29/20 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/0228 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78606

Abstract: A semiconductor device has a substrate with a semiconductor material. The semiconductor device includes a field effect transistor in and on the semiconductor material. The field effect transistor has a gate dielectric layer over the semiconductor material of the semiconductor device, and a gate over the gate dielectric layer. The gate dielectric layer includes a layer of nitrogen-rich silicon nitride immediately over the region for the channel, and under the gate.

公开(公告)号：US12211835B2

公开(公告)日：2025-01-28

申请号：US17462743

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Hiroyuki Tomomatsu

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/66 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

公开(公告)号：US20240405017A1

公开(公告)日：2024-12-05

申请号：US18325376

申请日：2023-05-30

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Sunglyong Kim ,  Kyoung Min Lee

IPC: H01L27/06 ,  H01L29/66

Abstract: A microelectronic device including an integrated boot diode and a depleted mode LDMOS transistor with a charge balance layer isolated from the body region and electrically in contact with a substrate. The connection of the charge balance layer of the depleted mode LDMOS transistor directly to the substrate or ground reference eliminates body diode turn-on from the body of the transistor to the drain which typically happens above approximately 0.7 volts. In addition, the depleted mode LDMOS transistor may separate a source contact from a body contact which allows a negative bias of the body with respect to the source. Typically, the source voltage is limited to approximately 7 volts before parasitic PNP turn on becomes a factor. By negatively biasing the body with respect to the source, the maximum source voltage of the depleted mode LDMOS transistor without PNP parasitic turn-on may be increased to approximately 30 V.

公开(公告)号：US12142639B2

公开(公告)日：2024-11-12

申请号：US18347234

申请日：2023-07-05

Applicant: Texas Instruments Incorporated

Inventor： Qhalid R S Fareed ,  Dong Seup Lee ,  Nicholas S. Dellas

IPC: H01L29/15 ,  H01L21/02

Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.

公开(公告)号：US20240363394A1

公开(公告)日：2024-10-31

申请号：US18141153

申请日：2023-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Sunglyong Kim ,  Meng-Chia Lee ,  Satoshi Suzuki ,  Seetharaman Sridhar

IPC: H01L21/761 ,  H01L27/088

CPC classification number: H01L21/761 ,  H01L27/088 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/66681

Abstract: Described examples include an integrated circuit having a substrate, a first doped region in the substrate having a first conductivity type, and a first epitaxial layer on the substrate, wherein the first doped region extends into the first epitaxial layer. The integrated circuit also has a second doped region in the first epitaxial layer having the first conductivity type, a second epitaxial layer on the first epitaxial layer, wherein the second doped region extends into the second epitaxial layer. The integrated circuit also has a well in the second epitaxial layer having a second conductivity type, and a first active device formed in the well.