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    BIASING ISOLATION REGION IN SEMICONDUCTOR SUBSTRATE
    32.
    发明公开
    BIASING ISOLATION REGION IN SEMICONDUCTOR SUBSTRATE 审中-公开

    公开(公告)号：US20230335547A1

    公开(公告)日：2023-10-19

    申请号：US18192956

    申请日：2023-03-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Orlando Lazaro ,  John Russell Broze ,  Timothy Bryan Merkin

    IPC: H01L27/06 ,  H01L27/088 ,  H03K17/687

    CPC classification number: H01L27/0629 ,  H01L27/088 ,  H03K17/6872

    Abstract: The present disclosure generally relates to biasing an isolation region in a semiconductor substrate. In an example, an integrated circuit includes a semiconductor substrate, a first rectifying device, and a second rectifying device. The semiconductor substrate has a first region, a second region, and a third region each being an opposite conductivity type from the semiconductor substrate. The first region and the second region are respective current terminals of a transistor. The first rectifying device has a first positive terminal and a first negative terminal. The first positive terminal is coupled to the first region, and the first negative terminal is coupled to the third region. The second rectifying device has a second positive terminal and a second negative terminal. The second positive terminal is coupled to a ground terminal, and the second negative terminal is coupled to the third region.

    Isolated power transfer via coupled oscillators
    33.
    发明授权
    Isolated power transfer via coupled oscillators 有权

    公开(公告)号：US11515839B2

    公开(公告)日：2022-11-29

    申请号：US17087356

    申请日：2020-11-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Orlando Lazaro

    IPC: H03B5/12 ,  H02J50/10

    Abstract: A system includes a power receiver including an oscillator with a first coil and a second coil. The oscillator includes a first field effect transistor (FET) having first gate, first source, and first drain terminals, the first drain terminal coupled to the first coil, the first coil adapted to be inductively coupled to a third coil in a power transmitter. The oscillator also includes a first capacitor coupled to the first coil. The oscillator includes a second FET having second gate, second source, and second drain terminals, the second gate terminal coupled to the first capacitor, the second source terminal coupled to the first source terminal, and the second drain terminal coupled to the second coil, the second coil adapted to be inductively coupled to a fourth coil in the power transmitter. The oscillator includes a second capacitor coupled to the first gate terminal and coupled to the second coil.

    Hybrid multi-level inverter and charge pump
    34.
    发明授权
    Hybrid multi-level inverter and charge pump 有权

    公开(公告)号：US11502619B1

    公开(公告)日：2022-11-15

    申请号：US17389926

    申请日：2021-07-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Orlando Lazaro ,  Yogesh Kumar Ramadass ,  Nan Xing

    IPC: H02M7/483 ,  H02M3/07 ,  H02M1/00

    Abstract: A method includes charging a capacitor of a power inverter to a direct current (DC) input voltage provided at an input terminal of the power inverter. The capacitor has a first terminal and a second terminal. The method also includes providing a first voltage at an output terminal of the power inverter at a first time by controlling one of either a set of input switches configured to selectively couple the first and second terminals to either the input terminal or to a ground terminal, or an output switch configured to selectively couple the output terminal to either the first terminal or the second terminal. The method further includes providing a second voltage at the output terminal at a second time by controlling the other of the set of input switches and the output switch.

    Three-level converter using an auxiliary switched capacitor circuit
    36.
    发明授权
    Three-level converter using an auxiliary switched capacitor circuit 有权

    公开(公告)号：US11101735B2

    公开(公告)日：2021-08-24

    申请号：US16584610

    申请日：2019-09-26

    Applicant: Texas Instruments Incorporated

    Inventor： Kevin Scoones ,  Orlando Lazaro ,  Alvaro Aguilar ,  Jeffrey Anthony Morroni ,  Reza Sharifi ,  Saurav Bandyopadhyay

    IPC: H02M3/158 ,  H02M7/483 ,  H02M1/00

    Abstract: In a described example, an apparatus includes a first switch coupled between a terminal for receiving an input voltage and a top plate node, and having a first control terminal; a second switch coupled between the top plate node and a switching node, and having a second control terminal; a third switch coupled between the switching node and a bottom plate node and having a third control terminal; a fourth switch coupled between the bottom plate node and a ground terminal, and having a fourth control terminal; a flying capacitor coupled between the top plate node and the bottom plate node; a fifth switch coupled between the top plate node and an auxiliary node; a sixth switch coupled between the auxiliary node and the bottom plate node; and an auxiliary capacitor coupled between the auxiliary control terminal and a ground terminal.

    Boost-back protection for power converter
    37.
    发明授权
    Boost-back protection for power converter 有权

    公开(公告)号：US10778099B1

    公开(公告)日：2020-09-15

    申请号：US16520015

    申请日：2019-07-23

    Applicant: Texas Instruments Incorporated

    Inventor： Austin James Womac ,  Siew Kuok Hoon ,  Orlando Lazaro

    IPC: H02M3/158 ,  H02M1/14 ,  H02J7/00 ,  H02M3/156

    Abstract: A device includes a power converter having an input coupled to a first node and an output coupled to an output terminal adapted to couple to a battery. A blocking transistor is coupled between a second node and the first node. A regulator has inputs coupled to the first node and the second node and an output coupled to a control node of the blocking transistor. The regulator is configured to control the blocking transistor to regulate a voltage drop across the blocking transistor based on a voltage between the first node and the second node. The regulator is also configured to turn off the blocking transistor in response to a voltage at the first node exceeding a voltage at the second node by at least a threshold to block boost-back current flowing from the output terminal to the second node.

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