-
公开(公告)号：US20150180594A1
公开(公告)日：2015-06-25
申请号：US14137366
申请日：2013-12-20
Inventor： Sudipto Chakraborty , Jens Graul
CPC classification number: H03L7/0802 , H03L7/0891 , H03L7/099 , H03L7/104 , H03L7/18 , H03L7/235 , H04B1/403 , H04B1/408 , H04B1/50
Abstract: A self-calibrating shared-component dual synthesizer includes, for example, two frequency synthesizers that are adapted to operate (respectively) in transmit (TX) and receive (RX) modes. Each synthesizer can be selectively arranged to vary and optimize the phase noise in accordance with the TX and RX requirements associated with each mode as well as independently optimized for flexible low area floorplan to achieve low power, spectral fidelity and reduced test time, low cost built in self-calibration. The two frequency synthesizers are also adapted to provide a built-in self-test signals used for intermodulation testing and calibration.
Abstract translation: 自校准共享部件双合成器包括例如适于在发射（TX）和接收（RX）模式中分别操作的两个频率合成器。 每个合成器可以选择性地布置成根据与每个模式相关联的TX和RX要求来改变和优化相位噪声，并且针对灵活的低面积平面图进行独立优化，以实现低功率，频谱保真度和缩短的测试时间，低成本内置 进行自校准。 两个频率合成器也适用于提供用于互调测试和校准的内置自测信号。
-
公开(公告)号：US20150015222A1
公开(公告)日：2015-01-15
申请号：US13938085
申请日：2013-07-09
Inventor： Vadim Valerievich Ivanov , Sudipto Chakraborty , Jens Graul
IPC: G05F1/46
CPC classification number: G05F1/56
Abstract: Voltage regulators are disclosed herein. An embodiment of a voltage regulator includes a MOS-type pass transistor, wherein a first node of the pass transistor is connectable to a voltage source and wherein a second node of the pass transistor is connected to the output of the voltage regulator. The voltage regulator also includes an error amplifier having a reference input and an output, the output being connected to the gate of the pass transistor, and the reference input being connected to a reference voltage source.
Abstract translation: 本文公开了电压调节器。 电压调节器的实施例包括MOS型通过晶体管，其中传输晶体管的第一节点可连接到电压源，并且其中传输晶体管的第二节点连接到电压调节器的输出端。 电压调节器还包括具有参考输入和输出的误差放大器，输出端连接到传输晶体管的栅极，参考输入端连接到参考电压源。
-
公开(公告)号：US12119789B2
公开(公告)日：2024-10-15
申请号：US18326746
申请日：2023-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudipto Chakraborty
IPC: H03F3/213 , H03B5/12 , H03F1/02 , H03F3/21 , H03F3/24 , H03F3/45 , H03G1/00 , H03G3/00 , H03G3/30 , H04B1/04
CPC classification number: H03B5/1212 , H03B5/1228 , H03B5/1265 , H03F1/0211 , H03F1/0277 , H03F3/211 , H03F3/213 , H03F3/245 , H03F3/45 , H03G1/0005 , H03G3/004 , H03G3/3042 , H04B2001/0416
Abstract: A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.
-
公开(公告)号：US20200153465A1
公开(公告)日：2020-05-14
申请号：US16735033
申请日：2020-01-06
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty , Jens Graul , Ram Pratap Aditham
Abstract: A wireless wake-up receiver includes multiple signal chains each signal chain being coupled to continuously receive a signal from a respective antenna and to provide a respective detected pattern at a signal chain output. Each signal chain includes a first path having a mixer-first architecture and operates in a bandpass-mode using differential signals. The wireless wake-up receiver also includes a digital correlator operable to receive the respective detected patterns and to determine whether one of the respective detected patterns is equal to a desired pattern.
-
公开(公告)号：US10389456B2
公开(公告)日：2019-08-20
申请号：US15248604
申请日：2016-08-26
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty
IPC: H04B17/29 , H04L12/801 , H04W24/08 , H04L27/38 , H04L27/34
Abstract: A wireless receiver is disclosed that includes a peak detector coupled to receive a plurality of phases of an input signal, said plurality being substantially in quadrature, and to provide a detector output and a demodulator comprising an analog comparator coupled to receive said detector output and to provide a comparator output.
-
Patent Agency Ranking
公开(公告)号：US20180376420A1
公开(公告)日：2018-12-27
申请号：US16120154
申请日：2018-08-31
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty , Ram Pratap Aditham
Abstract: A system of multiple concurrent receivers is described to process multiple narrow bandwidth wireless signals with arbitrary bandwidth and center frequency separation. These multiple receivers may provide a downconverted signal at the baseband frequency to process signal bandwidth using the lowest power consumption while using fully modular signal processing blocks operating at the low frequency. The concurrent receivers may operate from a single high frequency amplifier and may be derived from a low impedance point to reduce loading and improve scalability. The center frequency and bandwidth of each of the channels as well as phases of each of the channels may be independently reconfigured to achieve scalability, and on-chip test and calibration capability.
-
公开(公告)号：US10129059B2
公开(公告)日：2018-11-13
申请号：US15597986
申请日：2017-05-17
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty , Vinod Mukundagiri
Abstract: A multi-amplitude modulation receiver includes a signal coupler block coupled to a mixer array block receiving a first input signal from the signal coupler block and a second input from a LO circuit that provides N overlapping phase signals. Outputs of the N mixer elements are coupled to a baseband filter (BBF) block then to a decision threshold block including decision threshold elements including a signal input and at least one comparator receiving at least one VTH value. A phase ordering and mapper block selects M out of the N phases. A digital logic and control block is coupled to control a filter gain and corner frequency of the BBF block and control the VTH value for the decision threshold block which compares a signal received to the VTH value. Outputs from the decision threshold block are coupled inputs of an M-input decision combiner which provides a single data output.
-
公开(公告)号：US09667193B2
公开(公告)日：2017-05-30
申请号：US14447478
申请日：2014-07-30
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty
CPC classification number: H03B5/1215 , H03B1/00 , H03B5/08 , H03B5/1212 , H03B5/1228 , H03B5/125 , H03B5/1262 , H03B5/1296 , H03B2200/0082 , H03B2201/0266
Abstract: A wide tuning range oscillator system uses multiple active cores with cross-coupled transistors and multiple tapped inductors having windings that can be connected to circuit nodes. These active cores are connected to a pair of symmetric tapping points and are switched ON/OFF by biasing elements. Biasing schemes and the topology of the individual cross-coupled cores may be different from each other. The tapping points are symmetrically arranged around the center point of the inductor. One or more of the active cores may be enabled for tuning the center frequency of the oscillator system.
-
公开(公告)号：US09231625B2
公开(公告)日：2016-01-05
申请号：US14807079
申请日：2015-07-23
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty , David Le Deaut , Josef Einzinger , Jens Graul
CPC classification number: H03G3/3042 , H03F1/02 , H03F3/24 , H04B1/04 , H04B1/0458 , H04B1/10 , H04B1/44 , H04B2001/0408 , H04B2001/045
Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.
-
公开(公告)号：US09176188B2
公开(公告)日：2015-11-03
申请号：US14137994
申请日：2013-12-20
Inventor： Sudipto Chakraborty , Jens Graul
IPC: H04B3/46 , G01R31/317 , H04B17/00
CPC classification number: G01R31/31716 , G01R31/2822 , G01R31/3187 , H04B17/13 , H04B17/19
Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components.
Abstract translation: 芯片上的系统（SoC）包括收发器，包括具有功率放大器的发射机和具有信号缓冲器的接收机。 发射器和接收器中的至少一个具有可配置部分，其可被配置为产生波形范围（波形以及占空比）。 内置自检（BIST）逻辑的低成本耦合到收发器。 BIST逻辑可操作地校准收发器的可配置部分以产生具有小于阈值的幅度的选定谐波分量的波形。 可以通过选择具有低谐波分量的优化波形来动态地减少收发器消耗的电流。
-
-
-
-
-
-
-
-
-
Search Results
80
records
(took 0.019 seconds)
