公开(公告)号：US20200373395A1

公开(公告)日：2020-11-26

申请号：US16417735

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong ,  Jyun-Guan Jhou

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/765 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.

公开(公告)号：US10797174B2

公开(公告)日：2020-10-06

申请号：US16104692

申请日：2018-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Tai Chang ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Tzu-Chung Wang ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/033 ,  H01L21/02 ,  H01L23/532

Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.

公开(公告)号：US20200273997A1

公开(公告)日：2020-08-27

申请号：US16874539

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US10395937B2

公开(公告)日：2019-08-27

申请号：US15689334

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Dian-Hau Chen ,  Han-Ting Tsai ,  Tsung-Lin Lee ,  Chia-Cheng Ho ,  Ming-Shiang Lin

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L21/3115

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.