公开(公告)号：US11955425B2

公开(公告)日：2024-04-09

申请号：US18168043

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L23/522 ,  G06F30/39 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  G06F30/39 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/5221 ,  H01L23/528

Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

公开(公告)号：US20240113097A1

公开(公告)日：2024-04-04

申请号：US18522727

申请日：2023-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06

CPC classification number: H01L27/0207 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L21/823828

Abstract: An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.

公开(公告)号：US11855072B2

公开(公告)日：2023-12-26

申请号：US17850067

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L27/118 ,  H01L21/8238

CPC classification number: H01L27/0207 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L21/823828

Abstract: An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.

公开(公告)号：US11527651B2

公开(公告)日：2022-12-13

申请号：US17068162

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/423 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51 ,  H01L23/532 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/311

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

公开(公告)号：US10916498B2

公开(公告)日：2021-02-09

申请号：US15938484

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  G06F30/39

Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

公开(公告)号：US10804401B2

公开(公告)日：2020-10-13

申请号：US16734968

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw

IPC: H01L27/115 ,  H01L29/78 ,  H01L21/321 ,  H01L29/45 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/311

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

公开(公告)号：US10651170B2

公开(公告)日：2020-05-12

申请号：US15646962

申请日：2017-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lung Tung ,  Min-Chang Liang ,  Fang Chen

IPC: H01L27/08 ,  H01L27/12 ,  H01L29/06 ,  H01L49/02 ,  H01L21/84 ,  H01L21/761 ,  G06F17/50 ,  H01L21/762

Abstract: A semiconductor device includes a substrate, a dielectric layer over the substrate, a first resistor element embedded within the dielectric layer, a second resistor element embedded within the dielectric layer, a first doped well within the substrate, the first doped well being aligned with the first resistor element, and a second doped well within the substrate, the second doped well being aligned with the second resistor element, the second doped well being non-contiguous with the first doped well.

公开(公告)号：US20190371933A1

公开(公告)日：2019-12-05

申请号：US15993970

申请日：2018-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Jhon Jhy Liaw

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/321 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.