公开(公告)号：US11650493B2

公开(公告)日：2023-05-16

申请号：US17568037

申请日：2022-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Chun-Fu Yang ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/24 ,  G03F1/70 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F1/70 ,  G03F7/2004

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

公开(公告)号：US11531262B2

公开(公告)日：2022-12-20

申请号：US17083348

申请日：2020-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chang Lee ,  Pei-Cheng Hsu ,  Ta-Cheng Lien ,  Wen-Chang Hsueh

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/48

Abstract: A reflective mask blank includes a substrate, a reflective multilayer (RML) disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer has length or width dimensions smaller than the capping layer, and part of the capping layer is exposed by the absorber layer. The dimension of the absorber layer and the hard mask layer ranges between 146 cm to 148 cm. The dimensions of the substrate, the RML, and the capping layer range between 150 cm to 152 cm.

公开(公告)号：US20220260932A1

公开(公告)日：2022-08-18

申请号：US17481010

申请日：2021-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Ping-Hsun Lin ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F7/20 ,  C23C16/455

Abstract: Coated nanotubes and bundles of nanotubes are formed into membranes useful in optical assemblies in EUV photolithography systems. These optical assemblies are useful in methods for patterning materials on a semiconductor substrate. Such methods involve generating, in a UV lithography system, UV radiation. The UV radiation is passed through a coating layer of the optical assembly, e.g., a pellicle assembly. The UV radiation that has passed through the coating layer is passed through a matrix of individual nanotubes or matrix of nanotube bundles. UV radiation that passes through the matrix of individual nanotubes or matrix of nanotube bundles is reflected from a mask and received at a semiconductor substrate.

公开(公告)号：US11360384B2

公开(公告)日：2022-06-14

申请号：US16568028

申请日：2019-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Fu Yang ,  Pei-Cheng Hsu ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/82 ,  G03F7/20

Abstract: A method includes placing a photomask having a contamination on a surface thereof in a plasma processing chamber. The contaminated photomask is plasma processed in the plasma processing chamber to remove the contamination from the surface. The plasma includes oxygen plasma or hydrogen plasma.

公开(公告)号：US11327405B2

公开(公告)日：2022-05-10

申请号：US17080652

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Cheng Chen ,  Chia-Jen Chen ,  Hsin-Chang Lee ,  Shih-Ming Chang ,  Tran-Hui Shen ,  Yen-Cheng Ho ,  Chen-Shao Hsu

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78 ,  H01J37/317 ,  G03F1/76

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

公开(公告)号：US20220121103A1

公开(公告)日：2022-04-21

申请号：US17568037

申请日：2022-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Chun-Fu Yang ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/24 ,  G03F1/70 ,  G03F7/20

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

公开(公告)号：US20210294203A1

公开(公告)日：2021-09-23

申请号：US17340991

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Chien-Cheng Chen ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Pei-Cheng Hsu ,  Yih-Chen Su ,  Gaston Lee ,  Tran-Hui Shen

IPC: G03F1/24 ,  G03F7/20 ,  G03F1/54 ,  G03F1/38

Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.

公开(公告)号：US11029593B2

公开(公告)日：2021-06-08

申请号：US16660300

申请日：2019-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Chien-Cheng Chen ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Pei-Cheng Hsu ,  Yih-Chen Su ,  Gaston Lee ,  Tran-Hui Shen

IPC: G03F1/54 ,  G03F1/24 ,  G03F7/20 ,  G03F1/38 ,  G03F1/22

Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.

公开(公告)号：US11022874B2

公开(公告)日：2021-06-01

申请号：US16548273

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee

IPC: G03F1/26 ,  G03F1/38 ,  G03F1/34 ,  G03F1/80 ,  H01L21/266

Abstract: The present disclosure provides a mask. The mask includes a substrate; an etch stop layer disposed on the substrate, wherein the etch stop layer includes at least one of ruthenium oxide, tungsten nitride, and titanium nitride and is doped with at least one of phosphorous (P), calcium (Ca), and sodium (Na); and a material layer disposed on the etch stop layer and patterned to have an opening, wherein the etch stop layer completely covers a portion of the substrate within the opening.

公开(公告)号：US20210033960A1

公开(公告)日：2021-02-04

申请号：US16776046

申请日：2020-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Chun-Fu Yang ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/80 ,  G03F1/48 ,  G03F1/70 ,  G03F7/20

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.