公开(公告)号：US20190103437A1

公开(公告)日：2019-04-04

申请号：US16190608

申请日：2018-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Su ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Shih-Pei Chou

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an image sensor device. The image sensor device includes an image sensing element disposed within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element. The plurality of protrusions respectively include a sidewall having a first segment oriented at a first angle and a second segment over the first segment. The second segment is oriented at a second angle that is larger than the first angle. One or more absorption enhancement layers are arranged over and between the plurality of protrusions. The first angle and the second angle are acute angles measured through the substrate with respect to a horizontal plane that is parallel to a second side of the substrate opposite the first side.

公开(公告)号：US10163947B2

公开(公告)日：2018-12-25

申请号：US15803995

申请日：2017-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L21/00 ,  H01L27/146 ,  H01L31/18

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.

公开(公告)号：US10084056B1

公开(公告)日：2018-09-25

申请号：US15463088

申请日：2017-03-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Wen Hsu ,  Hung-Ling Shih ,  Jiech-Fun Lu

IPC: H01L21/302 ,  H01L29/49 ,  H01L27/06 ,  H01L21/311 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.

公开(公告)号：US09991303B2

公开(公告)日：2018-06-05

申请号：US14658465

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Wen Hsu ,  Ching-Chung Su ,  Cheng-Hsien Chou ,  Jiech-Fun Lu ,  Shih-Pei Chou ,  Yeur-Luen Tu

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor structure is provided. The image sensor device structure includes a substrate, and the substrate includes an array region and a peripheral region. The image sensor device structure includes an anti-reflection layer formed on the substrate and a buffer layer formed on the anti-reflection layer. The image sensor device structure includes a first etch stop layer formed on the buffer layer and a metal grid structure formed on the first etch stop layer. The image sensor device structure also includes a dielectric layer formed on the metal grid structure.

公开(公告)号：US09812477B2

公开(公告)日：2017-11-07

申请号：US15169994

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

公开(公告)号：US20160276384A1

公开(公告)日：2016-09-22

申请号：US15169994

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

Abstract translation: 本公开涉及一种方法，本公开涉及具有有源像素传感器的集成芯片，该有源像素传感器具有栅极介电保护层，其在制造期间减少对下面的栅极电介质层的损坏，以及相关联的形成方法。 在一些实施例中，集成芯片具有设置在衬底内的光电检测器和位于衬底上方的栅极结构。 栅介质保护层设置在衬底上并且沿着栅极结构的侧壁延伸到覆盖光电检测器的位置。 栅极绝缘保护层具有垂直于栅极结构的上表面的上表面。

公开(公告)号：US09412781B2

公开(公告)日：2016-08-09

申请号：US14867070

申请日：2015-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.

公开(公告)号：US11652025B2

公开(公告)日：2023-05-16

申请号：US17150048

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Ming Chyi Liu ,  Jiech-Fun Lu

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76898 ,  H01L27/14636 ,  H01L27/1464

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) including a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate, an insulating structure disposed along inner sidewalls of the semiconductor substrate, the inner sidewalls of the semiconductor substrate extending through the semiconductor substrate, a blocking layer disposed along inner sidewalls of the insulating structure, and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, the second portion extending from the first portion to the conductive structure and has a maximum width less than that of the first portion.

公开(公告)号：US11495489B2

公开(公告)日：2022-11-08

申请号：US16732696

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuan-Liang Liu ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/306

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

公开(公告)号：US20220285412A1

公开(公告)日：2022-09-08

申请号：US17328036

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Jiech-Fun Lu

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprises a plurality of photodetectors disposed within a substrate. A metal grid layer is disposed over the substrate. The metal grid layer comprises a metal grid structure overlying a central pixel region of the substrate. The metal grid layer continuously extends from the central pixel region to a peripheral pixel region of the substrate that laterally encloses the central pixel region. An upper metal structure is disposed over the metal grid layer. The upper metal structure overlies the peripheral pixel region. The upper metal structure is laterally offset from the metal grid structure. A lower surface of the upper metal structure is disposed vertically over an upper surface of the metal grid structure.