公开(公告)号：US20220367440A1

公开(公告)日：2022-11-17

申请号：US17876909

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Lun CHIEN ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/522

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

公开(公告)号：US20210242205A1

公开(公告)日：2021-08-05

申请号：US17028459

申请日：2020-09-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Pochun WANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  G06F30/392 ,  G06F30/31

Abstract: A semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: relative to a first direction, first and second active regions arranged in a stack according to CFET-type configuration; first and second contact structures correspondingly electrically coupled to the first active region; third and fourth contact structures correspondingly electrically coupled to the second active region; a first layer of metallization over the stack which includes alpha logic conductors configured for logic signals (alpha logic conductors), and power grid (PG) conductors, the alpha logic and PG conductors being non-overlapping of each other; and a layer of metallization below the stack which includes beta logic conductors which are non-overlapping of each other; and wherein, relative to a second direction, each of the alpha logic, PG and beta logic conductors at least partially overlap one or more of the first, second, third and fourth contact structures.

公开(公告)号：US20210098453A1

公开(公告)日：2021-04-01

申请号：US17120839

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20200328201A1

公开(公告)日：2020-10-15

申请号：US16837970

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Sing LI ,  Guo-Huei WU ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  G06F30/392

Abstract: An integrated circuit includes a first cell and a second cell. The first cell with a first cell height along a first direction includes a first active region and a second active region that extend in a second direction different from the first direction. The first active region overlaps the second active region in a layout view. The second cell with a second cell height includes a first plurality of active regions and a second plurality of active regions. The first plurality of active regions and the second plurality of active regions extend in the second direction and the first plurality of active regions overlap the second plurality of active regions, respectively, in the layout view. The first cell abuts the second cell, and the first active region is aligned with one of the first plurality of active regions in the layout view.

公开(公告)号：US20170323877A1

公开(公告)日：2017-11-09

申请号：US15145354

申请日：2016-05-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Ting-Wei CHIANG ,  Hui-Zhong ZHUANG ,  Pin-Dai SUE ,  Li-Chun TIEN

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L27/092 ,  H01L29/42376 ,  H01L2027/11875

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US20150067616A1

公开(公告)日：2015-03-05

申请号：US14011790

申请日：2013-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung HSU ,  Yuan-Te HOU ,  Li-Chun TIEN ,  Hui-Zhong ZHUANG ,  Fang-Yu FAN ,  Wen-Hao CHEN ,  Ting Yu CHEN

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Abstract translation: 一种方法包括将一个或多个单元与选择指南进行比较，并将满足选择准则的单元存储在非瞬态计算机可读存储介质中，以基于该比较创建单元库。 选择指南确定单元格内边界引脚的合适位置。

公开(公告)号：US20140073124A1

公开(公告)日：2014-03-13

申请号：US14079671

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Huei CHEN ,  Jung-Hsuan CHEN ,  Shao-Yu CHOU ,  Hung-Jen LIAO ,  Li-Chun TIEN

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.

Abstract translation: 一种方法包括在半导体衬底的有效区域上形成第一多个指状物。 第一多个指状物中的每一个具有在与有源区域的宽度方向平行的方向上延伸的相应长度。 第一多个指状物形成至少一个晶体管的至少一个栅极，该晶体管具有由有源区域的一部分形成的源极和漏极。 第一虚设多晶硅结构形成在第一多个指状物的外部之一和半导体衬底的第一边缘之间的有源区域的一部分上。 第二虚设多晶硅结构在第一虚设多晶硅结构和半导体衬底的第一边缘之间的半导体衬底之上。