公开(公告)号：US20230386912A1

公开(公告)日：2023-11-30

申请号：US18232718

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Kai CHANG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Keng-Chu LIN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L23/5226 ,  H01L23/53266 ,  H01L21/76816 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76876

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

公开(公告)号：US20230066265A1

公开(公告)日：2023-03-02

申请号：US17459803

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun CHEN ,  Pinyen LIN

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.

公开(公告)号：US20230061022A1

公开(公告)日：2023-03-02

申请号：US17459799

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Kai CHANG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Keng-Chu LIN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

公开(公告)号：US20230040346A1

公开(公告)日：2023-02-09

申请号：US17701402

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Huang-Lin CHAO ,  Chung-Liang CHENG ,  Pinyen LIN ,  Chun-Chun LIN ,  Tzu-Li LEE ,  Yu-Chia LIANG ,  Duen-Huei HOU ,  Wen-Chung LIU ,  Chun-I WU

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.

公开(公告)号：US20230017512A1

公开(公告)日：2023-01-19

申请号：US17377861

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Pinyen LIN ,  Fang-Wei LEE ,  Li-Te LIN ,  Han-yu LIN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/66

Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

公开(公告)号：US20230009077A1

公开(公告)日：2023-01-12

申请号：US17681346

申请日：2022-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Huan-Chieh SU ,  Lo-Heng CHANG ,  Shih-Chuan CHIU ,  Hsu-Kai CHANG ,  Ko-Feng CHEN ,  Keng-Chu LIN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second contact openings on the n- and p-type S/D regions, respectively, forming a carbon-based layer in the first and second contact openings, performing a remote plasma treatment with radicals on the carbon-based layer to form a remote plasma treated layer, selectively removing a portion of the remote plasma treated layer, forming a p-type work function metal (pWFM) silicide layer on the p-type S/D region, and forming an n-type work function metal (nWFM) silicide layer on the pWFM silicide layer and on the n-type S/D region.

公开(公告)号：US20220336623A1

公开(公告)日：2022-10-20

申请号：US17856892

申请日：2022-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Jung-Hao CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

公开(公告)号：US20220328324A1

公开(公告)日：2022-10-13

申请号：US17226332

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Yi-Shan CHEN ,  Chih-Kai YANG ,  Pinyen LIN

IPC: H01L21/311 ,  H01L21/66 ,  H01L21/033

Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.

公开(公告)号：US20210313449A1

公开(公告)日：2021-10-07

申请号：US16837432

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method also includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers. The method further includes removing a portion of the first semiconductor layers and second semiconductor layers to form a trench, and removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers. The method includes forming a dummy dielectric layer in the recess, and removing a portion of the dummy dielectric layer to form a cavity. The method also includes forming an inner spacer layer in the cavity.

公开(公告)号：US20210305409A1

公开(公告)日：2021-09-30

申请号：US17333676

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Li-Te LIN ,  Chung-Cheng WU ,  Gwan-Sin CHANG ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/49 ,  H01L29/40

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.